From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from inet-tsb5.toshiba.co.jp (inet-tsb5.toshiba.co.jp [202.33.96.24]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id 2AF36DDEE2 for ; Mon, 14 May 2007 17:56:40 +1000 (EST) Date: Mon, 14 May 2007 16:28:04 +0900 Message-ID: From: Tsutomu OWA To: Thomas Gleixner Subject: Re: [patch 4/4] powerpc 2.6.21-rt1: reduce scheduling latency by changing tlb flush size In-Reply-To: <1179125506.22481.297.camel@localhost.localdomain> References: <1179125506.22481.297.camel@localhost.localdomain> MIME-Version: 1.0 (generated by SEMI 1.14.4 - "Hosorogi") Content-Type: text/plain; charset=US-ASCII Cc: linuxppc-dev@ozlabs.org, mingo@elte.hu, linux-kernel@vger.kernel.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , At Mon, 14 May 2007 08:51:46 +0200, Thomas Gleixner wrote: > On Mon, 2007-05-14 at 15:38 +0900, Tsutomu OWA wrote: > > As I don't know how long it takes on other platforms, it would be better to > > enclose it within #ifdef CONFIG_PPC_CELLEB. > > Yes, that might be appropriate. Can you add this and resend please ? Certainly, and thanks for your comment. To reduce scheduling latecy by changing tlb flush size to 1. Since tlb flush on Celleb is done by calling (an) expensive hypervisor call(s), it takes a long time to flush tlbs and causes scheduing latency. Signed-off-by: Tsutomu OWA -- owa --- linux-2.6.21-rt1/include/asm-powerpc/tlbflush.h 2007-04-26 12:08:32.000000000 +0900 +++ rt/include/asm-powerpc/tlbflush.h 2007-05-14 16:12:47.000000000 +0900 @@ -25,7 +25,12 @@ struct mm_struct; #include #include +#if defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT) +/* Since tlb flush takes long time on Celleb, reduce it to 1 when Celleb && RT */ +#define PPC64_TLB_BATCH_NR 1 +#else #define PPC64_TLB_BATCH_NR 192 +#endif /* defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT) */ struct ppc64_tlb_batch { unsigned long index; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757377AbXENH4t (ORCPT ); Mon, 14 May 2007 03:56:49 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1754529AbXENH4n (ORCPT ); Mon, 14 May 2007 03:56:43 -0400 Received: from inet-tsb5.toshiba.co.jp ([202.33.96.24]:44521 "EHLO inet-tsb5.toshiba.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752264AbXENH4n (ORCPT ); Mon, 14 May 2007 03:56:43 -0400 Date: Mon, 14 May 2007 16:28:04 +0900 Message-ID: From: Tsutomu OWA To: Thomas Gleixner Cc: linuxppc-dev@ozlabs.org, linux-kernel@vger.kernel.org, mingo@elte.hu Subject: Re: [patch 4/4] powerpc 2.6.21-rt1: reduce scheduling latency by changing tlb flush size In-Reply-To: <1179125506.22481.297.camel@localhost.localdomain> References: <1179125506.22481.297.camel@localhost.localdomain> User-Agent: Wanderlust/2.8.1 (Something) Emacs/20.7 Mule/4.0 (HANANOEN) Organization: Software Engineering Center, TOSHIBA. MIME-Version: 1.0 (generated by SEMI 1.14.4 - "Hosorogi") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org At Mon, 14 May 2007 08:51:46 +0200, Thomas Gleixner wrote: > On Mon, 2007-05-14 at 15:38 +0900, Tsutomu OWA wrote: > > As I don't know how long it takes on other platforms, it would be better to > > enclose it within #ifdef CONFIG_PPC_CELLEB. > > Yes, that might be appropriate. Can you add this and resend please ? Certainly, and thanks for your comment. To reduce scheduling latecy by changing tlb flush size to 1. Since tlb flush on Celleb is done by calling (an) expensive hypervisor call(s), it takes a long time to flush tlbs and causes scheduing latency. Signed-off-by: Tsutomu OWA -- owa --- linux-2.6.21-rt1/include/asm-powerpc/tlbflush.h 2007-04-26 12:08:32.000000000 +0900 +++ rt/include/asm-powerpc/tlbflush.h 2007-05-14 16:12:47.000000000 +0900 @@ -25,7 +25,12 @@ struct mm_struct; #include #include +#if defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT) +/* Since tlb flush takes long time on Celleb, reduce it to 1 when Celleb && RT */ +#define PPC64_TLB_BATCH_NR 1 +#else #define PPC64_TLB_BATCH_NR 192 +#endif /* defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT) */ struct ppc64_tlb_batch { unsigned long index;