From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from inet-tsb5.toshiba.co.jp (inet-tsb5.toshiba.co.jp [202.33.96.24]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id 673FBDDF22 for ; Mon, 14 May 2007 16:38:53 +1000 (EST) Date: Mon, 14 May 2007 15:38:39 +0900 Message-ID: From: Tsutomu OWA To: linuxppc-dev@ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [patch 4/4] powerpc 2.6.21-rt1: reduce scheduling latency by changing tlb flush size In-Reply-To: References: MIME-Version: 1.0 (generated by SEMI 1.14.4 - "Hosorogi") Content-Type: text/plain; charset=US-ASCII Cc: mingo@elte.hu, tglx@linutronix.de List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Oopps, Subject was wrong.... resending it. Sorry. To reduce scheduling latecy by changing tlb flush size to 1. Since tlb flush on Celleb is done by calling (an) expensive hypervisor call(s), it takes a long time to flush tlbs and causes scheduing latency. As I don't know how long it takes on other platforms, it would be better to enclose it within #ifdef CONFIG_PPC_CELLEB. Signed-off-by: Tsutomu OWA -- owa diff -rup linux-2.6.21-rt1/include/asm-powerpc/tlbflush.h rt/include/asm-powerpc/tlbflush.h --- linux-2.6.21-rt1/include/asm-powerpc/tlbflush.h 2007-04-26 12:08:32.000000000 +0900 +++ rt/include/asm-powerpc/tlbflush.h 2007-05-07 14:23:50.000000000 +0900 @@ -25,7 +25,11 @@ struct mm_struct; #include #include +#ifdef CONFIG_PREEMPT_RT +#define PPC64_TLB_BATCH_NR 1 /* Since tlb flush takes long time, reduce it to 1 when RT */ +#else #define PPC64_TLB_BATCH_NR 192 +#endif /* CONFIG_PREEMPT_RT */ struct ppc64_tlb_batch { unsigned long index;