From mboxrd@z Thu Jan  1 00:00:00 1970
From: "yitian" <yitian.bu@tangramtek.com>
Subject: Re: [RESEND PATCH 1/1] ASoC: dwc: correct irq clear
	method
Date: Thu, 1 Oct 2015 10:39:09 +0800
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 <20150930181751.GT15635@sirena.org.uk>
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To: 'Mark Brown' <broonie@kernel.org>
Cc: alsa-devel@alsa-project.org, wsa@the-dreams.de, linux-kernel@vger.kernel.org, Andrew.Jackson@arm.com, lgirdwood@gmail.com, tiwai@suse.com, linux-arm-kernel@lists.infradead.org
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> From: linux-arm-kernel
> [mailto:linux-arm-kernel-bounces@lists.infradead.org] On Behalf Of Mark
> Brown
> Sent: Thursday, October 1, 2015 2:18 AM
> To: yitian <yitian.bu@tangramtek.com>
> Cc: alsa-devel@alsa-project.org; wsa@the-dreams.de;
> linux-kernel@vger.kernel.org; Andrew.Jackson@arm.com; tiwai@suse.com;
> lgirdwood@gmail.com; perex@perex.cz;
> linux-arm-kernel@lists.infradead.org
> Subject: Re: [RESEND PATCH 1/1] ASoC: dwc: correct irq clear method
> 
> On Tue, Sep 29, 2015 at 10:39:00PM +0800, yitian wrote:
> > from Designware I2S datasheet, irq is cleared by reading from
> > TOR/ROR registers, rather than by writing into them.
> 
> This doesn't apply against current code, please check and resend.
Hi Mark:

Thanks for your comments.
Maybe I misunderstand your meaning. Please correct me.

I synced up to latest kernel branch, the code is the same as what this patch
was
generated.

I checked designware I2S spec "version 1.08a June 2014", it specified that
the TOR
and ROR registers are read only and reading the last bit will clear tx/rx
overrun irq.

Also I have checked this register by writing its last bit, the overrun irq
is not cleared.
But if I read the last bit, the overrun irq is cleared. That means the spec
is correct.

Can you please let me know what else I should double check? Thanks.