From mboxrd@z Thu Jan 1 00:00:00 1970 From: Liam Girdwood Subject: Re: [PATCH 1/4] ASoC: tlv320aic3x: Optimize PLL programming in aic3x_set_bias_level Date: Sat, 11 Sep 2010 09:04:56 +0100 Message-ID: <1284192296.3409.2.camel@odin> References: <1284117812-8618-1-git-send-email-jhnikula@gmail.com> <20100910113650.GE7259@rakim.wolfsonmicro.main> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wy0-f179.google.com (mail-wy0-f179.google.com [74.125.82.179]) by alsa0.perex.cz (Postfix) with ESMTP id 83E5F244DE for ; Sat, 11 Sep 2010 10:05:00 +0200 (CEST) Received: by mail-wy0-f179.google.com with SMTP id 32so3691386wyb.38 for ; Sat, 11 Sep 2010 01:05:00 -0700 (PDT) In-Reply-To: <20100910113650.GE7259@rakim.wolfsonmicro.main> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: alsa-devel-bounces@alsa-project.org Errors-To: alsa-devel-bounces@alsa-project.org To: Mark Brown Cc: alsa-devel@alsa-project.org List-Id: alsa-devel@alsa-project.org On Fri, 2010-09-10 at 12:36 +0100, Mark Brown wrote: > On Fri, Sep 10, 2010 at 02:23:29PM +0300, Jarkko Nikula wrote: > > There is only need to enable/disable once the PLL when the bias is going > > between on, prepare, standby and off states. > > Acked-by: Mark Brown Applied. Thanks Liam -- Freelance Developer, SlimLogic Ltd ASoC and Voltage Regulator Maintainer. http://www.slimlogic.co.uk