* [PATCH 1/3] ASoC: wm8900: Fix wrong mask for setting DAC_CLKDIV/ADC_CLKDIV/LRCLK_MODE
@ 2011-10-16 15:27 Axel Lin
2011-10-16 15:29 ` [PATCH 2/3] ASoC: wm8900: Fix the mask defines Axel Lin
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Axel Lin @ 2011-10-16 15:27 UTC (permalink / raw)
To: linux-kernel; +Cc: Dimitris Papastamos, alsa-devel, Mark Brown, Liam Girdwood
After checking the datasheet, I think what we want to do here is to
clear the WM8900_REG_CLOCKING2_DAC_CLKDIV/WM8900_REG_CLOCKING2_ADC_CLKDIV/
WM8900_REG_DACCTRL_AIF_LRCLKRATE bits and then OR with div value.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
---
I'd appreciate if someone can test this serial of patches.
Thanks,
Axel
sound/soc/codecs/wm8900.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c
index 082040e..b16522f 100644
--- a/sound/soc/codecs/wm8900.c
+++ b/sound/soc/codecs/wm8900.c
@@ -844,17 +844,17 @@ static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
case WM8900_DAC_CLKDIV:
reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
snd_soc_write(codec, WM8900_REG_CLOCKING2,
- div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));
+ div | (reg & ~WM8900_REG_CLOCKING2_DAC_CLKDIV));
break;
case WM8900_ADC_CLKDIV:
reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
snd_soc_write(codec, WM8900_REG_CLOCKING2,
- div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));
+ div | (reg & ~WM8900_REG_CLOCKING2_ADC_CLKDIV));
break;
case WM8900_LRCLK_MODE:
reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
snd_soc_write(codec, WM8900_REG_DACCTRL,
- div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));
+ div | (reg & ~WM8900_REG_DACCTRL_AIF_LRCLKRATE));
break;
default:
return -EINVAL;
--
1.7.4.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/3] ASoC: wm8900: Fix the mask defines
2011-10-16 15:27 [PATCH 1/3] ASoC: wm8900: Fix wrong mask for setting DAC_CLKDIV/ADC_CLKDIV/LRCLK_MODE Axel Lin
@ 2011-10-16 15:29 ` Axel Lin
2011-10-16 15:30 ` [PATCH 3/3] ASoC: wm8900: Use snd_soc_update_bits for read-modify-write Axel Lin
2011-10-17 21:49 ` [PATCH 1/3] ASoC: wm8900: Fix wrong mask for setting DAC_CLKDIV/ADC_CLKDIV/LRCLK_MODE Mark Brown
2 siblings, 0 replies; 4+ messages in thread
From: Axel Lin @ 2011-10-16 15:29 UTC (permalink / raw)
To: linux-kernel; +Cc: Dimitris Papastamos, alsa-devel, Mark Brown, Liam Girdwood
Now we have done bitwise NOT against the mask bits for the defines of
WM8900_REG_CLOCKING1_BCLK_MASK,
WM8900_REG_CLOCKING1_OPCLK_MASK and WM8900_LRC_MASK.
But we don't have the bitwise NOT against the mask bits for the defines of
WM8900_REG_CLOCKING2_DAC_CLKDIV,
WM8900_REG_CLOCKING2_ADC_CLKDIV and WM8900_REG_DACCTRL_AIF_LRCLKRATE.
It is error prone to mix the inconsistent meaning for different mask defines.
So lets make the defines for each mask to be corresponding to the bits
defines in datasheet. Don't add extra "bitwise NOT" to the defines.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
---
sound/soc/codecs/wm8900.c | 14 +++++++-------
1 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c
index b16522f..86de396 100644
--- a/sound/soc/codecs/wm8900.c
+++ b/sound/soc/codecs/wm8900.c
@@ -110,8 +110,8 @@
#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
-#define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e)
-#define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
+#define WM8900_REG_CLOCKING1_BCLK_MASK 0x01e
+#define WM8900_REG_CLOCKING1_OPCLK_MASK 0x7000
#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
@@ -135,7 +135,7 @@
#define WM8900_REG_HPCTL1_HP_SHORT 0x08
#define WM8900_REG_HPCTL1_HP_SHORT2 0x04
-#define WM8900_LRC_MASK 0xfc00
+#define WM8900_LRC_MASK 0x03ff
struct wm8900_priv {
enum snd_soc_control_type control_type;
@@ -824,22 +824,22 @@ static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
case WM8900_BCLK_DIV:
reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
snd_soc_write(codec, WM8900_REG_CLOCKING1,
- div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
+ div | (reg & ~WM8900_REG_CLOCKING1_BCLK_MASK));
break;
case WM8900_OPCLK_DIV:
reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
snd_soc_write(codec, WM8900_REG_CLOCKING1,
- div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
+ div | (reg & ~WM8900_REG_CLOCKING1_OPCLK_MASK));
break;
case WM8900_DAC_LRCLK:
reg = snd_soc_read(codec, WM8900_REG_AUDIO4);
snd_soc_write(codec, WM8900_REG_AUDIO4,
- div | (reg & WM8900_LRC_MASK));
+ div | (reg & ~WM8900_LRC_MASK));
break;
case WM8900_ADC_LRCLK:
reg = snd_soc_read(codec, WM8900_REG_AUDIO3);
snd_soc_write(codec, WM8900_REG_AUDIO3,
- div | (reg & WM8900_LRC_MASK));
+ div | (reg & ~WM8900_LRC_MASK));
break;
case WM8900_DAC_CLKDIV:
reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
--
1.7.4.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 3/3] ASoC: wm8900: Use snd_soc_update_bits for read-modify-write
2011-10-16 15:27 [PATCH 1/3] ASoC: wm8900: Fix wrong mask for setting DAC_CLKDIV/ADC_CLKDIV/LRCLK_MODE Axel Lin
2011-10-16 15:29 ` [PATCH 2/3] ASoC: wm8900: Fix the mask defines Axel Lin
@ 2011-10-16 15:30 ` Axel Lin
2011-10-17 21:49 ` [PATCH 1/3] ASoC: wm8900: Fix wrong mask for setting DAC_CLKDIV/ADC_CLKDIV/LRCLK_MODE Mark Brown
2 siblings, 0 replies; 4+ messages in thread
From: Axel Lin @ 2011-10-16 15:30 UTC (permalink / raw)
To: linux-kernel; +Cc: Dimitris Papastamos, alsa-devel, Mark Brown, Liam Girdwood
Use snd_soc_update_bits for read-modify-write register access instead of
open-coding it using snd_soc_read and snd_soc_write
Signed-off-by: Axel Lin <axel.lin@gmail.com>
---
sound/soc/codecs/wm8900.c | 109 +++++++++++++++++---------------------------
1 files changed, 42 insertions(+), 67 deletions(-)
diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c
index 86de396..3d0dc15 100644
--- a/sound/soc/codecs/wm8900.c
+++ b/sound/soc/codecs/wm8900.c
@@ -742,26 +742,20 @@ static int wm8900_set_fll(struct snd_soc_codec *codec,
{
struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
struct _fll_div fll_div;
- unsigned int reg;
if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
return 0;
/* The digital side should be disabled during any change. */
- reg = snd_soc_read(codec, WM8900_REG_POWER1);
- snd_soc_write(codec, WM8900_REG_POWER1,
- reg & (~WM8900_REG_POWER1_FLL_ENA));
+ snd_soc_update_bits(codec, WM8900_REG_POWER1,
+ WM8900_REG_POWER1_FLL_ENA, 0);
/* Disable the FLL? */
if (!freq_in || !freq_out) {
- reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
- snd_soc_write(codec, WM8900_REG_CLOCKING1,
- reg & (~WM8900_REG_CLOCKING1_MCLK_SRC));
-
- reg = snd_soc_read(codec, WM8900_REG_FLLCTL1);
- snd_soc_write(codec, WM8900_REG_FLLCTL1,
- reg & (~WM8900_REG_FLLCTL1_OSC_ENA));
-
+ snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
+ WM8900_REG_CLOCKING1_MCLK_SRC, 0);
+ snd_soc_update_bits(codec, WM8900_REG_FLLCTL1,
+ WM8900_REG_FLLCTL1_OSC_ENA, 0);
wm8900->fll_in = freq_in;
wm8900->fll_out = freq_out;
@@ -796,15 +790,14 @@ static int wm8900_set_fll(struct snd_soc_codec *codec,
else
snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
- reg = snd_soc_read(codec, WM8900_REG_POWER1);
- snd_soc_write(codec, WM8900_REG_POWER1,
- reg | WM8900_REG_POWER1_FLL_ENA);
+ snd_soc_update_bits(codec, WM8900_REG_POWER1,
+ WM8900_REG_POWER1_FLL_ENA,
+ WM8900_REG_POWER1_FLL_ENA);
reenable:
- reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
- snd_soc_write(codec, WM8900_REG_CLOCKING1,
- reg | WM8900_REG_CLOCKING1_MCLK_SRC);
-
+ snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
+ WM8900_REG_CLOCKING1_MCLK_SRC,
+ WM8900_REG_CLOCKING1_MCLK_SRC);
return 0;
}
@@ -818,43 +811,35 @@ static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_codec *codec = codec_dai->codec;
- unsigned int reg;
switch (div_id) {
case WM8900_BCLK_DIV:
- reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
- snd_soc_write(codec, WM8900_REG_CLOCKING1,
- div | (reg & ~WM8900_REG_CLOCKING1_BCLK_MASK));
+ snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
+ WM8900_REG_CLOCKING1_BCLK_MASK, div);
break;
case WM8900_OPCLK_DIV:
- reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
- snd_soc_write(codec, WM8900_REG_CLOCKING1,
- div | (reg & ~WM8900_REG_CLOCKING1_OPCLK_MASK));
+ snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
+ WM8900_REG_CLOCKING1_OPCLK_MASK, div);
break;
case WM8900_DAC_LRCLK:
- reg = snd_soc_read(codec, WM8900_REG_AUDIO4);
- snd_soc_write(codec, WM8900_REG_AUDIO4,
- div | (reg & ~WM8900_LRC_MASK));
+ snd_soc_update_bits(codec, WM8900_REG_AUDIO4,
+ WM8900_LRC_MASK, div);
break;
case WM8900_ADC_LRCLK:
- reg = snd_soc_read(codec, WM8900_REG_AUDIO3);
- snd_soc_write(codec, WM8900_REG_AUDIO3,
- div | (reg & ~WM8900_LRC_MASK));
+ snd_soc_update_bits(codec, WM8900_REG_AUDIO3,
+ WM8900_LRC_MASK, div);
break;
case WM8900_DAC_CLKDIV:
- reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
- snd_soc_write(codec, WM8900_REG_CLOCKING2,
- div | (reg & ~WM8900_REG_CLOCKING2_DAC_CLKDIV));
+ snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
+ WM8900_REG_CLOCKING2_DAC_CLKDIV, div);
break;
case WM8900_ADC_CLKDIV:
- reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
- snd_soc_write(codec, WM8900_REG_CLOCKING2,
- div | (reg & ~WM8900_REG_CLOCKING2_ADC_CLKDIV));
+ snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
+ WM8900_REG_CLOCKING2_ADC_CLKDIV, div);
break;
case WM8900_LRCLK_MODE:
- reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
- snd_soc_write(codec, WM8900_REG_DACCTRL,
- div | (reg & ~WM8900_REG_DACCTRL_AIF_LRCLKRATE));
+ snd_soc_update_bits(codec, WM8900_REG_DACCTRL,
+ WM8900_REG_DACCTRL_AIF_LRCLKRATE, div);
break;
default:
return -EINVAL;
@@ -1037,12 +1022,12 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec,
switch (level) {
case SND_SOC_BIAS_ON:
/* Enable thermal shutdown */
- reg = snd_soc_read(codec, WM8900_REG_GPIO);
- snd_soc_write(codec, WM8900_REG_GPIO,
- reg | WM8900_REG_GPIO_TEMP_ENA);
- reg = snd_soc_read(codec, WM8900_REG_ADDCTL);
- snd_soc_write(codec, WM8900_REG_ADDCTL,
- reg | WM8900_REG_ADDCTL_TEMP_SD);
+ snd_soc_update_bits(codec, WM8900_REG_GPIO,
+ WM8900_REG_GPIO_TEMP_ENA,
+ WM8900_REG_GPIO_TEMP_ENA);
+ snd_soc_update_bits(codec, WM8900_REG_ADDCTL,
+ WM8900_REG_ADDCTL_TEMP_SD,
+ WM8900_REG_ADDCTL_TEMP_SD);
break;
case SND_SOC_BIAS_PREPARE:
@@ -1205,26 +1190,16 @@ static int wm8900_probe(struct snd_soc_codec *codec)
wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
/* Latch the volume update bits */
- snd_soc_write(codec, WM8900_REG_LINVOL,
- snd_soc_read(codec, WM8900_REG_LINVOL) | 0x100);
- snd_soc_write(codec, WM8900_REG_RINVOL,
- snd_soc_read(codec, WM8900_REG_RINVOL) | 0x100);
- snd_soc_write(codec, WM8900_REG_LOUT1CTL,
- snd_soc_read(codec, WM8900_REG_LOUT1CTL) | 0x100);
- snd_soc_write(codec, WM8900_REG_ROUT1CTL,
- snd_soc_read(codec, WM8900_REG_ROUT1CTL) | 0x100);
- snd_soc_write(codec, WM8900_REG_LOUT2CTL,
- snd_soc_read(codec, WM8900_REG_LOUT2CTL) | 0x100);
- snd_soc_write(codec, WM8900_REG_ROUT2CTL,
- snd_soc_read(codec, WM8900_REG_ROUT2CTL) | 0x100);
- snd_soc_write(codec, WM8900_REG_LDAC_DV,
- snd_soc_read(codec, WM8900_REG_LDAC_DV) | 0x100);
- snd_soc_write(codec, WM8900_REG_RDAC_DV,
- snd_soc_read(codec, WM8900_REG_RDAC_DV) | 0x100);
- snd_soc_write(codec, WM8900_REG_LADC_DV,
- snd_soc_read(codec, WM8900_REG_LADC_DV) | 0x100);
- snd_soc_write(codec, WM8900_REG_RADC_DV,
- snd_soc_read(codec, WM8900_REG_RADC_DV) | 0x100);
+ snd_soc_update_bits(codec, WM8900_REG_LINVOL, 0x100, 0x100);
+ snd_soc_update_bits(codec, WM8900_REG_RINVOL, 0x100, 0x100);
+ snd_soc_update_bits(codec, WM8900_REG_LOUT1CTL, 0x100, 0x100);
+ snd_soc_update_bits(codec, WM8900_REG_ROUT1CTL, 0x100, 0x100);
+ snd_soc_update_bits(codec, WM8900_REG_LOUT2CTL, 0x100, 0x100);
+ snd_soc_update_bits(codec, WM8900_REG_ROUT2CTL, 0x100, 0x100);
+ snd_soc_update_bits(codec, WM8900_REG_LDAC_DV, 0x100, 0x100);
+ snd_soc_update_bits(codec, WM8900_REG_RDAC_DV, 0x100, 0x100);
+ snd_soc_update_bits(codec, WM8900_REG_LADC_DV, 0x100, 0x100);
+ snd_soc_update_bits(codec, WM8900_REG_RADC_DV, 0x100, 0x100);
/* Set the DAC and mixer output bias */
snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
--
1.7.4.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/3] ASoC: wm8900: Fix wrong mask for setting DAC_CLKDIV/ADC_CLKDIV/LRCLK_MODE
2011-10-16 15:27 [PATCH 1/3] ASoC: wm8900: Fix wrong mask for setting DAC_CLKDIV/ADC_CLKDIV/LRCLK_MODE Axel Lin
2011-10-16 15:29 ` [PATCH 2/3] ASoC: wm8900: Fix the mask defines Axel Lin
2011-10-16 15:30 ` [PATCH 3/3] ASoC: wm8900: Use snd_soc_update_bits for read-modify-write Axel Lin
@ 2011-10-17 21:49 ` Mark Brown
2 siblings, 0 replies; 4+ messages in thread
From: Mark Brown @ 2011-10-17 21:49 UTC (permalink / raw)
To: Axel Lin; +Cc: linux-kernel, Dimitris Papastamos, Liam Girdwood, alsa-devel
On Sun, Oct 16, 2011 at 11:27:55PM +0800, Axel Lin wrote:
> After checking the datasheet, I think what we want to do here is to
> clear the WM8900_REG_CLOCKING2_DAC_CLKDIV/WM8900_REG_CLOCKING2_ADC_CLKDIV/
> WM8900_REG_DACCTRL_AIF_LRCLKRATE bits and then OR with div value.
Applied all, thanks.
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2011-10-17 21:49 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2011-10-16 15:27 [PATCH 1/3] ASoC: wm8900: Fix wrong mask for setting DAC_CLKDIV/ADC_CLKDIV/LRCLK_MODE Axel Lin
2011-10-16 15:29 ` [PATCH 2/3] ASoC: wm8900: Fix the mask defines Axel Lin
2011-10-16 15:30 ` [PATCH 3/3] ASoC: wm8900: Use snd_soc_update_bits for read-modify-write Axel Lin
2011-10-17 21:49 ` [PATCH 1/3] ASoC: wm8900: Fix wrong mask for setting DAC_CLKDIV/ADC_CLKDIV/LRCLK_MODE Mark Brown
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