From: Mark Brown <broonie@opensource.wolfsonmicro.com>
To: Liam Girdwood <lrg@ti.com>
Cc: alsa-devel@alsa-project.org, patches@opensource.wolfsonmicro.com,
Mark Brown <broonie@opensource.wolfsonmicro.com>
Subject: [PATCH] ASoC: Fix WM8996 24.576MHz clock operation
Date: Sat, 10 Dec 2011 20:39:07 +0800 [thread overview]
Message-ID: <1323520747-5532-1-git-send-email-broonie@opensource.wolfsonmicro.com> (raw)
Record the clock after the divider as that is what all SYSCLK users see.
Without this the other clock configuration in the device comes out at
half rate.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
---
sound/soc/codecs/wm8996.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/sound/soc/codecs/wm8996.c b/sound/soc/codecs/wm8996.c
index 41cc9d2..8f88f5a 100644
--- a/sound/soc/codecs/wm8996.c
+++ b/sound/soc/codecs/wm8996.c
@@ -2043,6 +2043,7 @@ static int wm8996_set_sysclk(struct snd_soc_dai *dai,
break;
case 24576000:
ratediv = WM8996_SYSCLK_DIV;
+ wm8996->sysclk /= 2;
case 12288000:
snd_soc_update_bits(codec, WM8996_AIF_RATE,
WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
--
1.7.7.3
reply other threads:[~2011-12-10 19:00 UTC|newest]
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