From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark Brown Subject: [PATCH] ASoC: Fix WM8996 24.576MHz clock operation Date: Sat, 10 Dec 2011 20:39:07 +0800 Message-ID: <1323520747-5532-1-git-send-email-broonie@opensource.wolfsonmicro.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from opensource.wolfsonmicro.com (opensource.wolfsonmicro.com [80.75.67.52]) by alsa0.perex.cz (Postfix) with ESMTP id 04BD92470A for ; Sat, 10 Dec 2011 20:00:17 +0100 (CET) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: alsa-devel-bounces@alsa-project.org Errors-To: alsa-devel-bounces@alsa-project.org To: Liam Girdwood Cc: alsa-devel@alsa-project.org, patches@opensource.wolfsonmicro.com, Mark Brown List-Id: alsa-devel@alsa-project.org Record the clock after the divider as that is what all SYSCLK users see. Without this the other clock configuration in the device comes out at half rate. Signed-off-by: Mark Brown --- sound/soc/codecs/wm8996.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/sound/soc/codecs/wm8996.c b/sound/soc/codecs/wm8996.c index 41cc9d2..8f88f5a 100644 --- a/sound/soc/codecs/wm8996.c +++ b/sound/soc/codecs/wm8996.c @@ -2043,6 +2043,7 @@ static int wm8996_set_sysclk(struct snd_soc_dai *dai, break; case 24576000: ratediv = WM8996_SYSCLK_DIV; + wm8996->sysclk /= 2; case 12288000: snd_soc_update_bits(codec, WM8996_AIF_RATE, WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE); -- 1.7.7.3