[PATCH v2 0/4] ASoC: Intel: Enable BDW/HSW SRAM power gating

[PATCH v2 0/4] ASoC: Intel: Enable BDW/HSW SRAM power gating

[Jie Yang]

Hi Mark,

Here is the patch series for enable Intel Broadwell/Haswell ADSP
SRAM power gating feature.

Patches 0001~0002 merge wcp DRAM regions and correct the SRAM bit shift
for it;

Patch 0003 add dummy read to workaround SRAM write missing bytes issue;

Patch 0004 will make SRAM start with all memory banks disabled, and
enabled required banks during boot procedure.

thanks,
Keyon

Changes in v2:
* remove the Add persistent area alloc patch, for it is not so related
  with power gating feature.

Jie Yang (4):
  ASoC: Intel: Merge wild cat point ADSP DRAM regions
  ASoC: Intel: Use a table for ADSP SRAM shift
  ASoC: Intel: Add dummy read for SRAM block enable
  ASoC: Intel: Start with all memory banks disabled

 sound/soc/intel/sst-haswell-dsp.c | 61 +++++++++++++++++++++++++++++----------
 1 file changed, 46 insertions(+), 15 deletions(-)

-- 
1.8.3.2

[PATCH v2 1/4] ASoC: Intel: Merge wild cat point ADSP DRAM regions

[Jie Yang]

Merge D-SRAM0 D-SRAM1 D-SRAM2 to D-SRAM, for wild cat point ADSP mem regions.

Signed-off-by: Jie Yang <yang.jie@intel.com>
---
 sound/soc/intel/sst-haswell-dsp.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/sound/soc/intel/sst-haswell-dsp.c b/sound/soc/intel/sst-haswell-dsp.c
index 535f517..4720382 100644
--- a/sound/soc/intel/sst-haswell-dsp.c
+++ b/sound/soc/intel/sst-haswell-dsp.c
@@ -313,9 +313,7 @@ static const struct sst_adsp_memregion lp_region[] = {
 
 /* wild cat point ADSP mem regions */
 static const struct sst_adsp_memregion wpt_region[] = {
-	{0x00000, 0x40000, 8, SST_MEM_DRAM}, /* D-SRAM0 - 8 * 32kB */
-	{0x40000, 0x80000, 8, SST_MEM_DRAM}, /* D-SRAM1 - 8 * 32kB */
-	{0x80000, 0xA0000, 4, SST_MEM_DRAM}, /* D-SRAM2 - 4 * 32kB */
+	{0x00000, 0xA0000, 20, SST_MEM_DRAM}, /* D-SRAM0,D-SRAM1,D-SRAM2 - 20 * 32kB */
 	{0xA0000, 0xF0000, 10, SST_MEM_IRAM}, /* I-SRAM - 10 * 32kB */
 };
 
-- 
1.8.3.2

[PATCH v2 2/4] ASoC: Intel: Use a table for ADSP SRAM shift

[Jie Yang]

Use a table for ADSP IRAM/DRAM bit shift.

Signed-off-by: Jie Yang <yang.jie@intel.com>
---
 sound/soc/intel/sst-haswell-dsp.c | 39 +++++++++++++++++++++++++++++----------
 1 file changed, 29 insertions(+), 10 deletions(-)

diff --git a/sound/soc/intel/sst-haswell-dsp.c b/sound/soc/intel/sst-haswell-dsp.c
index 4720382..40bb020 100644
--- a/sound/soc/intel/sst-haswell-dsp.c
+++ b/sound/soc/intel/sst-haswell-dsp.c
@@ -337,21 +337,40 @@ static int hsw_acpi_resource_map(struct sst_dsp *sst, struct sst_pdata *pdata)
 	return 0;
 }
 
+struct sst_sram_shift {
+	u32 dev_id;	/* SST Device IDs  */
+	u32 iram_shift;
+	u32 dram_shift;
+};
+
+static const struct sst_sram_shift sram_shift[] = {
+	{SST_DEV_ID_LYNX_POINT, 6, 16}, /* lp */
+	{SST_DEV_ID_WILDCAT_POINT, 2, 12}, /* wpt */
+};
 static u32 hsw_block_get_bit(struct sst_mem_block *block)
 {
-	u32 bit = 0, shift = 0;
+	u32 bit = 0, shift = 0, index;
+	struct sst_dsp *sst = block->dsp;
 
-	switch (block->type) {
-	case SST_MEM_DRAM:
-		shift = 16;
-		break;
-	case SST_MEM_IRAM:
-		shift = 6;
-		break;
-	default:
-		return 0;
+	for (index = 0; index < ARRAY_SIZE(sram_shift); index++) {
+		if (sram_shift[index].dev_id == sst->id)
+			break;
 	}
 
+	if (index < ARRAY_SIZE(sram_shift)) {
+		switch (block->type) {
+		case SST_MEM_DRAM:
+			shift = sram_shift[index].dram_shift;
+			break;
+		case SST_MEM_IRAM:
+			shift = sram_shift[index].iram_shift;
+			break;
+		default:
+			shift = 0;
+		}
+	} else
+		shift = 0;
+
 	bit = 1 << (block->index + shift);
 
 	return bit;
-- 
1.8.3.2

[PATCH v2 3/4] ASoC: Intel: Add dummy read for SRAM block enable

[Jie Yang]

Add dummy read after each block enable, to workaround
SRAM write missing bytes issue.

Signed-off-by: Jie Yang <yang.jie@intel.com>
---
 sound/soc/intel/sst-haswell-dsp.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/sound/soc/intel/sst-haswell-dsp.c b/sound/soc/intel/sst-haswell-dsp.c
index 40bb020..61dbf91 100644
--- a/sound/soc/intel/sst-haswell-dsp.c
+++ b/sound/soc/intel/sst-haswell-dsp.c
@@ -376,6 +376,17 @@ static u32 hsw_block_get_bit(struct sst_mem_block *block)
 	return bit;
 }
 
+/*dummy read a SRAM block.*/
+static void sst_mem_block_dummy_read(struct sst_mem_block *block)
+{
+	u32 size;
+	u8 tmp_buf[4];
+	struct sst_dsp *sst = block->dsp;
+
+	size = block->size > 4 ? 4 : block->size;
+	memcpy_fromio(tmp_buf, sst->addr.lpe + block->offset, size);
+}
+
 /* enable 32kB memory block - locks held by caller */
 static int hsw_block_enable(struct sst_mem_block *block)
 {
@@ -395,6 +406,8 @@ static int hsw_block_enable(struct sst_mem_block *block)
 	/* wait 18 DSP clock ticks */
 	udelay(10);
 
+	/*add a dummy read before the SRAM block is written, otherwise the writing may miss bytes sometimes.*/
+	sst_mem_block_dummy_read(block);
 	return 0;
 }
 
-- 
1.8.3.2

[PATCH v2 4/4] ASoC: Intel: Start with all memory banks disabled

[Jie Yang]

All required banks are enabled during boot procedure.

Signed-off-by: Jie Yang <yang.jie@intel.com>
---
 sound/soc/intel/sst-haswell-dsp.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/sound/soc/intel/sst-haswell-dsp.c b/sound/soc/intel/sst-haswell-dsp.c
index 61dbf91..1819327 100644
--- a/sound/soc/intel/sst-haswell-dsp.c
+++ b/sound/soc/intel/sst-haswell-dsp.c
@@ -518,8 +518,9 @@ static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata)
 		}
 	}
 
-	/* set default power gating mask */
-	writel(0x0, sst->addr.pci_cfg + SST_VDRTCTL0);
+	/* set default power gating control, enable power gating control for all blocks. that is,
+	can't be accessed, please enable each block before accessing. */
+	writel(0xffffffff, sst->addr.pci_cfg + SST_VDRTCTL0);
 
 	return 0;
 }
-- 
1.8.3.2

Re: [PATCH v2 3/4] ASoC: Intel: Add dummy read for SRAM block enable

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 166 bytes --]

On Mon, Jul 14, 2014 at 05:11:11PM +0800, Jie Yang wrote:
> Add dummy read after each block enable, to workaround
> SRAM write missing bytes issue.

Applied, thanks.

[-- Attachment #1.2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

[-- Attachment #2: Type: text/plain, Size: 0 bytes --]

Re: [PATCH v2 1/4] ASoC: Intel: Merge wild cat point ADSP DRAM regions

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 156 bytes --]

On Mon, Jul 14, 2014 at 05:11:09PM +0800, Jie Yang wrote:
> Merge D-SRAM0 D-SRAM1 D-SRAM2 to D-SRAM, for wild cat point ADSP mem regions.

Applied, thanks.

[-- Attachment #1.2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

[-- Attachment #2: Type: text/plain, Size: 0 bytes --]

Re: [PATCH v2 2/4] ASoC: Intel: Use a table for ADSP SRAM shift

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 120 bytes --]

On Mon, Jul 14, 2014 at 05:11:10PM +0800, Jie Yang wrote:
> Use a table for ADSP IRAM/DRAM bit shift.

Applied, thanks.

[-- Attachment #1.2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

[-- Attachment #2: Type: text/plain, Size: 0 bytes --]

Re: [PATCH v2 4/4] ASoC: Intel: Start with all memory banks disabled

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 132 bytes --]

On Mon, Jul 14, 2014 at 05:11:12PM +0800, Jie Yang wrote:
> All required banks are enabled during boot procedure.

Applied, thanks.

[-- Attachment #1.2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

[-- Attachment #2: Type: text/plain, Size: 0 bytes --]