From: Bard Liao <bardliao@realtek.com>
To: broonie@kernel.org, lgirdwood@gmail.com
Cc: oder_chiou@realtek.com, alsa-devel@alsa-project.org,
lars@metafoo.de, koro.chen@mediatek.com, john.lin@realtek.com,
Bard Liao <bardliao@realtek.com>,
flove@realtek.com
Subject: [PATCH 1/2] ASoC: rt5677: fixed wrong DMIC ref clock
Date: Tue, 28 Apr 2015 11:27:39 +0800 [thread overview]
Message-ID: <1430191660-2959-1-git-send-email-bardliao@realtek.com> (raw)
DMIC clock source is not from codec system clock directly. it is
generated from the division of system clock. And it should be 256 *
sample rate of AIF1.
Signed-off-by: Bard Liao <bardliao@realtek.com>
---
sound/soc/codecs/rt5677.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c
index fbe16ba..dca64ae 100644
--- a/sound/soc/codecs/rt5677.c
+++ b/sound/soc/codecs/rt5677.c
@@ -917,7 +917,7 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w,
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
- int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
+ int idx = rl6231_calc_dmic_clk(rt5677->lrck[RT5677_AIF1] << 8);
if (idx < 0)
dev_err(codec->dev, "Failed to set DMIC clock\n");
--
1.8.1.1.439.g50a6b54
next reply other threads:[~2015-04-28 3:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-28 3:27 Bard Liao [this message]
2015-04-28 3:27 ` [PATCH 2/2] ASoC: rt5677: add i2s asrc clk src selection Bard Liao
2015-04-29 11:20 ` Mark Brown
2015-04-29 11:20 ` [PATCH 1/2] ASoC: rt5677: fixed wrong DMIC ref clock Mark Brown
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