From mboxrd@z Thu Jan 1 00:00:00 1970 From: mengdong.lin@intel.com Subject: [PATCH v2 2/3] ALSA: hda - remove controller dependency on i915 power well for Baytrail/Braswell Date: Tue, 28 Apr 2015 20:43:10 +0800 Message-ID: <1430224990-22229-1-git-send-email-mengdong.lin@intel.com> References: <4530387c0b63ccfafb5dbb3399a39b4093651c48.1429880424.git.mengdong.lin@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by alsa0.perex.cz (Postfix) with ESMTP id 79F2F26129B for ; Tue, 28 Apr 2015 14:32:47 +0200 (CEST) In-Reply-To: <4530387c0b63ccfafb5dbb3399a39b4093651c48.1429880424.git.mengdong.lin@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org To: alsa-devel@alsa-project.org, tiwai@suse.de Cc: Mengdong Lin List-Id: alsa-devel@alsa-project.org From: Mengdong Lin For Baytrail (Valleyview) and Braswell (Cherryview), not the HD-A controller but only the display codec is in the shared power well with gfx. Signed-off-by: Mengdong Lin diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 1b688ba..e73dc34 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -1903,8 +1903,9 @@ static int azx_probe_continue(struct azx *chip) * display codec needs the power and it can be released after probe. */ if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { - /* Assume the controller needs the power by default */ - chip->need_i915_power = 1; + /* Baytral/Braswell controllers don't need this power */ + if (pci->device != 0x0f04 && pci->device != 0x2284) + chip->need_i915_power = 1; #ifdef CONFIG_SND_HDA_I915 err = hda_i915_init(hda); diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c index 5f44f60..7b2744c 100644 --- a/sound/pci/hda/patch_hdmi.c +++ b/sound/pci/hda/patch_hdmi.c @@ -2335,6 +2335,14 @@ static int patch_generic_hdmi(struct hda_codec *codec) intel_haswell_fixup_enable_dp12(codec); } + /* For Valleyview/Cherryview, the codec is in the display power well. + * For Haswell/Broadwell, the controller is also in the power well and + * can cover codec power request, and so need not set this flag. + * For previous platforms, there is no such power well feature. + */ + if (is_valleyview_plus(codec)) + codec->core.need_i915_power = 1; + if (is_haswell_plus(codec) || is_valleyview_plus(codec)) codec->depop_delay = 0; -- 1.9.1