From: jeeja.kp@intel.com
To: alsa-devel@alsa-project.org
Cc: tiwai@suse.de, Jayachandran B <jayachandran.b@intel.com>,
patches.audio@intel.com, broonie@kernel.org,
liam.r.girdwood@intel.com, Jeeja KP <jeeja.kp@intel.com>
Subject: [PATCH 1/6] ASoC: Intel: Common: Update dsp register poll implementation
Date: Mon, 2 Jan 2017 09:50:02 +0530 [thread overview]
Message-ID: <1483330807-9518-2-git-send-email-jeeja.kp@intel.com> (raw)
In-Reply-To: <1483330807-9518-1-git-send-email-jeeja.kp@intel.com>
From: Jeeja KP <jeeja.kp@intel.com>
Poll implementation is not quite accurate, especially for smaller
values of timeout or timeout values close to the actual timeout needed
Use jiffies to set the timeout value and time_before() to get the
accurate time. So update the dsp register poll implementation to
provide accurate timeout using jiffies.
Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
---
sound/soc/intel/common/sst-dsp.c | 52 ++++++++++++++++++++--------------------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/sound/soc/intel/common/sst-dsp.c b/sound/soc/intel/common/sst-dsp.c
index c00ede4..11c0805 100644
--- a/sound/soc/intel/common/sst-dsp.c
+++ b/sound/soc/intel/common/sst-dsp.c
@@ -252,44 +252,44 @@ void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset,
EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced);
int sst_dsp_register_poll(struct sst_dsp *ctx, u32 offset, u32 mask,
- u32 target, u32 timeout, char *operation)
+ u32 target, u32 time, char *operation)
{
- int time, ret;
u32 reg;
- bool done = false;
+ unsigned long timeout;
+ int k = 0, s = 500;
/*
- * we will poll for couple of ms using mdelay, if not successful
- * then go to longer sleep using usleep_range
+ * split the loop into sleeps of varying resolution. more accurately,
+ * the range of wakeups are:
+ * Phase 1(first 5ms): min sleep 0.5ms; max sleep 1ms.
+ * Phase 2:( 5ms to 10ms) : min sleep 0.5ms; max sleep 10ms
+ * (usleep_range (500, 1000) and usleep_range(5000, 10000) are
+ * both possible in this phase depending on whether k > 10 or not).
+ * Phase 3: (beyond 10 ms) min sleep 5ms; max sleep 10ms.
*/
- /* check if set state successful */
- for (time = 0; time < 5; time++) {
- if ((sst_dsp_shim_read_unlocked(ctx, offset) & mask) == target) {
- done = true;
- break;
- }
- mdelay(1);
+ timeout = jiffies + msecs_to_jiffies(time);
+ while (((sst_dsp_shim_read_unlocked(ctx, offset) & mask) != target)
+ && time_before(jiffies, timeout)) {
+ k++;
+ if (k > 10)
+ s = 5000;
+
+ usleep_range(s, 2*s);
}
- if (done == false) {
- /* sleeping in 10ms steps so adjust timeout value */
- timeout /= 10;
+ reg = sst_dsp_shim_read_unlocked(ctx, offset);
- for (time = 0; time < timeout; time++) {
- if ((sst_dsp_shim_read_unlocked(ctx, offset) & mask) == target)
- break;
+ if ((reg & mask) == target) {
+ dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s successful\n",
+ reg, operation);
- usleep_range(5000, 10000);
- }
+ return 0;
}
- reg = sst_dsp_shim_read_unlocked(ctx, offset);
- dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s %s\n", reg, operation,
- (time < timeout) ? "successful" : "timedout");
- ret = time < timeout ? 0 : -ETIME;
-
- return ret;
+ dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s timedout\n",
+ reg, operation);
+ return -ETIME;
}
EXPORT_SYMBOL_GPL(sst_dsp_register_poll);
--
2.5.0
next prev parent reply other threads:[~2017-01-02 4:09 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-02 4:20 [PATCH 0/6] ASoC: Intel: Skylake: Driver updates on DSP firmware jeeja.kp
2017-01-02 4:20 ` jeeja.kp [this message]
2017-01-06 18:16 ` Applied "ASoC: Intel: Common: Update dsp register poll implementation" to the asoc tree Mark Brown
2017-01-02 4:20 ` [PATCH 2/6] ASoC: Intel: bxtn: Use DSP poll API to poll FW status jeeja.kp
2017-01-06 18:16 ` Applied "ASoC: Intel: bxtn: Use DSP poll API to poll FW status" to the asoc tree Mark Brown
2017-01-02 4:20 ` [PATCH 3/6] ASoC: Intel: Skylake: Clean up manifest info jeeja.kp
2017-01-06 18:16 ` Applied "ASoC: Intel: Skylake: Clean up manifest info" to the asoc tree Mark Brown
2017-01-02 4:20 ` [PATCH 4/6] ASoC: Intel: Skylake: Release FW ctx in cleanup jeeja.kp
2017-01-06 18:16 ` Applied "ASoC: Intel: Skylake: Release FW ctx in cleanup" to the asoc tree Mark Brown
2017-01-02 4:20 ` [PATCH 5/6] ASoC: Intel: bxtn: Fix to store the FW/Library context at boot jeeja.kp
2017-01-06 18:14 ` Mark Brown
2017-01-09 8:23 ` Jeeja KP
2017-03-07 12:57 ` Applied "ASoC: Intel: bxtn: Store the FW/Library context at boot" to the asoc tree Mark Brown
2017-01-02 4:20 ` [PATCH 6/6] ASoC: Intel: bxtn: optimize ROM init retries jeeja.kp
2017-03-07 12:57 ` Applied "ASoC: Intel: bxtn: optimize ROM init retries" to the asoc tree Mark Brown
2017-01-02 9:08 ` [PATCH 0/6] ASoC: Intel: Skylake: Driver updates on DSP firmware Vinod Koul
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