diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index 4448ab6..e676391c 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -852,6 +852,8 @@ static void haswell_verify_D0(struct hda_codec *codec,
 	/* For Haswell, the converter 1/2 may keep in D3 state after bootup,
 	 * thus pins could only choose converter 0 for use. Make sure the
 	 * converters are in correct power state */
+	printk(KERN_ERR "@@@ cvt_nid power state: %d\n", snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0));
+	printk(KERN_ERR "@@@ nid power state: %d\n", snd_hda_check_power_state(codec, nid, AC_PWRST_D0));
 	if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
 		snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
 
@@ -2470,13 +2472,13 @@ static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
 				unsigned int power_state)
 {
+	snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
+	snd_hda_codec_set_power_to_all(codec, fg, power_state);
+
 	if (power_state == AC_PWRST_D0) {
 		intel_haswell_enable_all_pins(codec, false);
 		intel_haswell_fixup_enable_dp12(codec);
 	}
-
-	snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
-	snd_hda_codec_set_power_to_all(codec, fg, power_state);
 }
 
 /* There is a fixed mapping between audio pin node and display port.