From: Bard Liao <bardliao@realtek.com>
To: broonie@kernel.org, lgirdwood@gmail.com
Cc: oder_chiou@realtek.com, jack.yu@realtek.com,
alsa-devel@alsa-project.org, shumingf@realtek.com,
Bard Liao <bardliao@realtek.com>,
flove@realtek.com
Subject: [PATCH] ASoC: rt5670: improve PLL function's stability
Date: Thu, 17 May 2018 13:54:08 +0800 [thread overview]
Message-ID: <1526536448-1603-1-git-send-email-bardliao@realtek.com> (raw)
Set PR-38 register to 0x1fe1 will make PLL function more stable.
Signed-off-by: Bard Liao <bardliao@realtek.com>
---
sound/soc/codecs/rt5670.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/rt5670.c b/sound/soc/codecs/rt5670.c
index dc7df33..732ef92 100644
--- a/sound/soc/codecs/rt5670.c
+++ b/sound/soc/codecs/rt5670.c
@@ -71,7 +71,7 @@ static const struct regmap_range_cfg rt5670_ranges[] = {
static const struct reg_sequence init_list[] = {
{ RT5670_PR_BASE + 0x14, 0x9a8a },
- { RT5670_PR_BASE + 0x38, 0x3ba1 },
+ { RT5670_PR_BASE + 0x38, 0x1fe1 },
{ RT5670_PR_BASE + 0x3d, 0x3640 },
{ 0x8a, 0x0123 },
};
--
2.7.4
next reply other threads:[~2018-05-17 5:54 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-17 5:54 Bard Liao [this message]
2018-05-17 17:12 ` Applied "ASoC: rt5670: improve PLL function's stability" to the asoc tree Mark Brown
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