From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark Brown Subject: Re: AT32AP7000 (AVR32) + WM8510 Date: Mon, 26 May 2008 10:45:24 +0100 Message-ID: <20080526094523.GA18721@sirena.org.uk> References: <200805221120.08815.geoffrey@pager.net> <20080522224840.GA31117@sirena.org.uk> <200805221811.31770.geoffrey@pager.net> <200805231756.00609.geoffrey@pager.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from cassiel.sirena.org.uk (cassiel.sirena.org.uk [80.68.93.111]) by alsa0.perex.cz (Postfix) with ESMTP id E421A103820 for ; Mon, 26 May 2008 11:45:25 +0200 (CEST) Content-Disposition: inline In-Reply-To: <200805231756.00609.geoffrey@pager.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: alsa-devel-bounces@alsa-project.org Errors-To: alsa-devel-bounces@alsa-project.org To: Geoffrey Wossum Cc: alsa-devel@alsa-project.org List-Id: alsa-devel@alsa-project.org On Fri, May 23, 2008 at 05:56:00PM -0500, Geoffrey Wossum wrote: > First, I changed it so the AVR32 provided the BCLK and FRAME. I could never > get the WM8510 to generate what looked like proper FRAMES. I did continue > using the WM8510's PLL to generate the DAC clock. With the AVR32 providing > the clocks, I at least got some noise out of it. The frame clock rate generated by the WM8510 will be 1/256 of the system clock, which should be configured to 256 times the sample rate using the PLL and dividers. > Finally, I really had to lie in the wm8510 code and say that it supported a > minimum of 2 channels, and a maximum of 2 channels. This makes sense from > the data sheet, since it still wants a left and a right channel of data, and > just throws one away. Yes, that's right. I've applied your changes to the driver - thanks! > I had to change the WM8510's format to say that it wanted big endian. Should > the CODEC (and platform and machine) be setup just to say that it uses > SNDRV_PCM_FMTBIT_S16 instead of SNDRV_PCM_FMTBIT_S16_LE/BE? Looks from > sound/pcm.h this should just do the Right Thing. Yes, it does look reasonable - I'll investigate. > Like I said before, it generated a 44.1 kHz frame no matter the BCLK divider > or the word length were set to. The frame clock is independent of both those options - I assume you are using a static system clock? > Thanks for the help! As soon as I get the code cleaned up some, I'll > contribute the AVR32 platform driver code. That would be excellent.