Re: snd soc spi read/write

Takashi Iwai
2011-08-10T11:54:34Z

At Wed, 10 Aug 2011 01:04:48 +0900,
Mark Brown wrote:
>
> On Tue, Aug 09, 2011 at 11:41:30AM +0800, Scott Jiang wrote:
>
> > There are three methods:
> > 1. pass different registers to snd_soc_read and snd_soc_write. But
> > snd_kcontrol and snd_soc_dapm_widget can't work because I pass only
> > one register.
> > 2. deal with this bit in hw_read, but this will be deprecated by
> > others whose chip doesn't have this bit.
> > 3. I'd like to use SND_SOC_CUS type, but it has been removed since
> > linux 3.0. I suggest we can reserve this type, considering SPI is a
> > simple "de facto" standard.
>
> No, like I say we just need to teach regmap about this stuff. It's not
> that odd, it's just your hardware designers seem to want to consume
> extra bandwidth on the control bus for some reason AFAICT as it looks
> like all the registers are 0x8xx.

Actually we should handle the register index only in the lower byte
for these devices. For example, ad193x has raw registers ranged from
0 to 0x10 with 0x800 high byte, while cs4271 has from 0 to 0x08 with
0x2000 high byte. So the raw register fits with flat array cache
well.

And, 16bit register value is needed only for SPI. For I2C, the upper
byte is anyway dropped.

Takashi