* [PATCH 1/2] ASoC: wm_adsp: Set ADSP1 clock rate to match sys clock
@ 2013-01-17 13:11 Chris Rattray
2013-01-17 13:11 ` [PATCH 2/2] ASoC: wm2200: Set system clock control register is adsp structs Chris Rattray
2013-01-18 6:17 ` [PATCH 1/2] ASoC: wm_adsp: Set ADSP1 clock rate to match sys clock Mark Brown
0 siblings, 2 replies; 5+ messages in thread
From: Chris Rattray @ 2013-01-17 13:11 UTC (permalink / raw)
To: broonie; +Cc: alsa-devel, patches, lrg, Chris Rattray
Sets the ADSP1 clock rate to match the system clock
rate. To support this the codec driver provides
details of register containing the system clock
control bits.
Signed-off-by: Chris Rattray <crattray@opensource.wolfsonmicro.com>
---
sound/soc/codecs/wm_adsp.c | 35 +++++++++++++++++++++++++++++++++++
sound/soc/codecs/wm_adsp.h | 3 +++
2 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c
index 9a3f220..739dab6 100644
--- a/sound/soc/codecs/wm_adsp.c
+++ b/sound/soc/codecs/wm_adsp.c
@@ -75,6 +75,8 @@
#define ADSP1_CONTROL_30 0x24
#define ADSP1_CONTROL_31 0x26
+#define ADSP1_CLOCKING 38
+
/*
* ADSP1 Control 19
*/
@@ -103,6 +105,13 @@
#define ADSP1_START_SHIFT 0 /* DSP1_START */
#define ADSP1_START_WIDTH 1 /* DSP1_START */
+/*
+ * ADSP1 Control 31
+ */
+#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
+#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
+#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
+
#define ADSP2_CONTROL 0
#define ADSP2_CLOCKING 1
#define ADSP2_STATUS1 4
@@ -817,12 +826,38 @@ int wm_adsp1_event(struct snd_soc_dapm_widget *w,
struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
struct wm_adsp *dsp = &dsps[w->shift];
int ret;
+ int val;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
ADSP1_SYS_ENA, ADSP1_SYS_ENA);
+ /*
+ * For simplicity set the DSP clock rate to be the
+ * SYSCLK rate rather than making it configurable.
+ */
+ if(dsp->sysclk_reg) {
+ ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
+ if (ret != 0) {
+ adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
+ ret);
+ return ret;
+ }
+
+ val = (val & dsp->sysclk_mask)
+ >> dsp->sysclk_shift;
+
+ ret = regmap_update_bits(dsp->regmap,
+ dsp->base + ADSP1_CLOCKING,
+ ADSP1_CLK_SEL_MASK, val);
+ if (ret != 0) {
+ adsp_err(dsp, "Failed to set clock rate: %d\n",
+ ret);
+ return ret;
+ }
+ }
+
ret = wm_adsp_load(dsp);
if (ret != 0)
goto err;
diff --git a/sound/soc/codecs/wm_adsp.h b/sound/soc/codecs/wm_adsp.h
index 41206d7..cb8871a 100644
--- a/sound/soc/codecs/wm_adsp.h
+++ b/sound/soc/codecs/wm_adsp.h
@@ -40,6 +40,9 @@ struct wm_adsp {
struct regmap *regmap;
int base;
+ int sysclk_reg;
+ int sysclk_mask;
+ int sysclk_shift;
struct list_head alg_regions;
--
1.7.2.5
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/2] ASoC: wm2200: Set system clock control register is adsp structs
2013-01-17 13:11 [PATCH 1/2] ASoC: wm_adsp: Set ADSP1 clock rate to match sys clock Chris Rattray
@ 2013-01-17 13:11 ` Chris Rattray
2013-01-18 6:17 ` [PATCH 1/2] ASoC: wm_adsp: Set ADSP1 clock rate to match sys clock Mark Brown
1 sibling, 0 replies; 5+ messages in thread
From: Chris Rattray @ 2013-01-17 13:11 UTC (permalink / raw)
To: broonie; +Cc: alsa-devel, patches, lrg, Chris Rattray
Allows ADSP control code to set the dsp clock rate to match the
sys clock rate.
Signed-off-by: Chris Rattray <crattray@opensource.wolfsonmicro.com>
---
sound/soc/codecs/wm2200.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/sound/soc/codecs/wm2200.c b/sound/soc/codecs/wm2200.c
index 5259ebd..0181444 100644
--- a/sound/soc/codecs/wm2200.c
+++ b/sound/soc/codecs/wm2200.c
@@ -2205,6 +2205,9 @@ static int wm2200_i2c_probe(struct i2c_client *i2c,
wm2200->dsp[i].num = i + 1;
wm2200->dsp[i].dev = &i2c->dev;
wm2200->dsp[i].regmap = wm2200->regmap;
+ wm2200->dsp[i].sysclk_reg = WM2200_CLOCKING_3;
+ wm2200->dsp[i].sysclk_mask = WM2200_SYSCLK_FREQ_MASK;
+ wm2200->dsp[i].sysclk_shift = WM2200_SYSCLK_FREQ_SHIFT;
}
wm2200->dsp[0].base = WM2200_DSP1_CONTROL_1;
--
1.7.2.5
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] ASoC: wm_adsp: Set ADSP1 clock rate to match sys clock
2013-01-17 13:11 [PATCH 1/2] ASoC: wm_adsp: Set ADSP1 clock rate to match sys clock Chris Rattray
2013-01-17 13:11 ` [PATCH 2/2] ASoC: wm2200: Set system clock control register is adsp structs Chris Rattray
@ 2013-01-18 6:17 ` Mark Brown
1 sibling, 0 replies; 5+ messages in thread
From: Mark Brown @ 2013-01-18 6:17 UTC (permalink / raw)
To: Chris Rattray; +Cc: alsa-devel, patches, lrg
On Thu, Jan 17, 2013 at 01:11:46PM +0000, Chris Rattray wrote:
> #define ADSP1_CONTROL_30 0x24
> #define ADSP1_CONTROL_31 0x26
>
> +#define ADSP1_CLOCKING 38
> +/*
> + * ADSP1 Control 31
> + */
> +#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
> +#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
> +#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
You just called this ADSP1_CLOCKING above, using a different style to
the other register #defines too (and of course there's already one for
the helpfully named ADSP1 Control 31...).
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] ASoC: wm_adsp: Set ADSP1 clock rate to match sys clock
@ 2013-01-18 8:43 Chris Rattray
2013-01-18 8:46 ` Mark Brown
0 siblings, 1 reply; 5+ messages in thread
From: Chris Rattray @ 2013-01-18 8:43 UTC (permalink / raw)
To: broonie; +Cc: alsa-devel, patches, lgirdwood, Chris Rattray
Sets the ADSP1 clock rate to match the system clock
rate. To support this the codec driver provides
details of register containing the system clock
control bits.
Signed-off-by: Chris Rattray <crattray@opensource.wolfsonmicro.com>
---
sound/soc/codecs/wm_adsp.c | 33 +++++++++++++++++++++++++++++++++
sound/soc/codecs/wm_adsp.h | 3 +++
2 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c
index 9a3f220..56bd6ba 100644
--- a/sound/soc/codecs/wm_adsp.c
+++ b/sound/soc/codecs/wm_adsp.c
@@ -103,6 +103,13 @@
#define ADSP1_START_SHIFT 0 /* DSP1_START */
#define ADSP1_START_WIDTH 1 /* DSP1_START */
+/*
+ * ADSP1 Control 31
+ */
+#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
+#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
+#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
+
#define ADSP2_CONTROL 0
#define ADSP2_CLOCKING 1
#define ADSP2_STATUS1 4
@@ -817,12 +824,38 @@ int wm_adsp1_event(struct snd_soc_dapm_widget *w,
struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
struct wm_adsp *dsp = &dsps[w->shift];
int ret;
+ int val;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
ADSP1_SYS_ENA, ADSP1_SYS_ENA);
+ /*
+ * For simplicity set the DSP clock rate to be the
+ * SYSCLK rate rather than making it configurable.
+ */
+ if(dsp->sysclk_reg) {
+ ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
+ if (ret != 0) {
+ adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
+ ret);
+ return ret;
+ }
+
+ val = (val & dsp->sysclk_mask)
+ >> dsp->sysclk_shift;
+
+ ret = regmap_update_bits(dsp->regmap,
+ dsp->base + ADSP1_CONTROL_31,
+ ADSP1_CLK_SEL_MASK, val);
+ if (ret != 0) {
+ adsp_err(dsp, "Failed to set clock rate: %d\n",
+ ret);
+ return ret;
+ }
+ }
+
ret = wm_adsp_load(dsp);
if (ret != 0)
goto err;
diff --git a/sound/soc/codecs/wm_adsp.h b/sound/soc/codecs/wm_adsp.h
index 41206d7..cb8871a 100644
--- a/sound/soc/codecs/wm_adsp.h
+++ b/sound/soc/codecs/wm_adsp.h
@@ -40,6 +40,9 @@ struct wm_adsp {
struct regmap *regmap;
int base;
+ int sysclk_reg;
+ int sysclk_mask;
+ int sysclk_shift;
struct list_head alg_regions;
--
1.7.2.5
^ permalink raw reply related [flat|nested] 5+ messages in thread
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2013-01-18 6:17 ` [PATCH 1/2] ASoC: wm_adsp: Set ADSP1 clock rate to match sys clock Mark Brown
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