From: Mark Brown <broonie@kernel.org>
To: Oder Chiou <oder_chiou@realtek.com>
Cc: alsa-devel@alsa-project.org, lgirdwood@gmail.com,
john.lin@realtek.com, anatol@google.com, bardliao@realtek.com,
benzh@google.com, flove@realtek.com
Subject: Re: [PATCH 3/3] ASoC: rt5677: Adjust the routing of "PLL1"
Date: Mon, 22 Dec 2014 18:41:33 +0000 [thread overview]
Message-ID: <20141222184133.GL17800@sirena.org.uk> (raw)
In-Reply-To: <1418969461-22494-3-git-send-email-oder_chiou@realtek.com>
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On Fri, Dec 19, 2014 at 02:11:01PM +0800, Oder Chiou wrote:
> Adjust the routing of "PLL1"
Again this isn't a good description - what is being adjusted and why?
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next prev parent reply other threads:[~2014-12-22 18:41 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-19 6:10 [PATCH 1/3] ASoC: rt5677: Revise the filter powers Oder Chiou
2014-12-19 6:11 ` [PATCH 2/3] ASoC: rt5677: Add the ASRC support Oder Chiou
2014-12-19 6:11 ` [PATCH 3/3] ASoC: rt5677: Adjust the routing of "PLL1" Oder Chiou
2014-12-22 18:41 ` Mark Brown [this message]
2014-12-22 18:40 ` [PATCH 1/3] ASoC: rt5677: Revise the filter powers Mark Brown
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