From mboxrd@z Thu Jan  1 00:00:00 1970
From: Nicolin Chen <nicoleotsuka@gmail.com>
Subject: Re: Freescale iMX6SL SSI (I2S master mode) Rising edge
 vs Falling edge
Date: Thu, 28 May 2015 00:09:44 -0700
Message-ID: <20150528070943.GA3532@Asurada>
References: <5566BD87.6040505@gmail.com>
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To: Xuebing Wang <xbing6@gmail.com>
Cc: alsa-devel@alsa-project.org, niranjan Patil <Niranjan.Patil@infocus.com>, fabio Estevam <festevam@gmail.com>, richard Jiang <Richard.Jiang@infocus.com>
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On Thu, May 28, 2015 at 03:02:31PM +0800, Xuebing Wang wrote:

> According to iMX6SL reference manual, 'TSCKP = 1' means "Data clocked out on
> *falling* edge of bit clock." (for I2S master mode), rather than "Data on
> rising edge of bclk in the comments". This means this comment in the source
> code is *partially* WRONG, am I correct?

As you can see, it says "clock out on falling edge" which means
for the receiver is still latching the data at the rising edge.

Nicolin