From mboxrd@z Thu Jan 1 00:00:00 1970 From: Nicolin Chen Subject: Re: [PATCH] ASoC: fsl-asoc-card: add wm8960 support Date: Wed, 12 Aug 2015 15:27:36 -0700 Message-ID: <20150812222735.GA57015@Asurada-CZ80> References: <20150812034257.GA2980@Asurada-CZ80> <20150812044505.GA21786@shlinux2> <20150812064053.GA2807@Asurada-CZ80> <20150812073859.GB21786@shlinux2> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-pa0-f47.google.com (mail-pa0-f47.google.com [209.85.220.47]) by alsa0.perex.cz (Postfix) with ESMTP id 597C32608ED for ; Thu, 13 Aug 2015 00:27:42 +0200 (CEST) Received: by pacrr5 with SMTP id rr5so23223833pac.3 for ; Wed, 12 Aug 2015 15:27:41 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20150812073859.GB21786@shlinux2> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org To: Zidan Wang Cc: fabio.estevam@freescale.com, alsa-devel@alsa-project.org, tiwai@suse.com, timur@tabi.org, broonie@kernel.org List-Id: alsa-devel@alsa-project.org On Wed, Aug 12, 2015 at 03:39:00PM +0800, Zidan Wang wrote: > On Tue, Aug 11, 2015 at 11:40:54PM -0700, Nicolin Chen wrote: > > On Wed, Aug 12, 2015 at 12:45:10PM +0800, Zidan Wang wrote: > > > > > > > + /* > > > > > + * for imx6ul we should set SAI2_MCLK_DIR to enable > > > > > + * codec MCLK > > > > > + */ > > > > > + if (of_device_is_compatible(np, "fsl,imx6ul-evk-wm8960")) > > > > > + regmap_update_bits(priv->gpr, 4, 1 << 20, 1 << 20); > > > > > > What's this SAI2_MCLK_DIR? Can you provide the description of it? > > > SAI2_MCLK_DIR: SD1_CLK data direction control when sai2.MCLK is selected (ALT2) > > > 0 SD1_CLK output driver is disabled when configured for ALT2 > > > 1 SD1_CLK output driver is enabled when configured for ALT2 > > > > > We are using SAI2 now, so we should enable SAI2_MCLK_DIR. If we want to > > > use SAI1 and SAI3, we should also enable SAI1_MCLK_DIR and SAI3_MCLK_DIR. > > > I don't consider SAI1 and SAI3 case, should i add it like below: > > > > Yes. Just think about a general interface/configuration that can > > satisfy all the MCLK cases you can imagine. > > And I still don't understand the meaning of this MCLK at all. > > Does it indicate SAI's MCLK or an MCLK for external CODEC chips? > > Will it be possible that a user needs this MCLK bit to be unset? > For imx6ul-evk, MCLK for wm8960 CODEC chips and SAI's MCLK is the same pin. > So it should always be set for SAI. Since the MCLK is driven to the external CODEC chip, it should be similar to the CLKO for wm8962 on the imx6qdl-sabresd board. So this configuration might be included in the clock tree in my opinion. And I Just checked the Reference Manual, it seems the direction could be totally set to input by leaving this bit unset: MCLK outputs via the SD1_CLK pad of IOMUX when setting this bit in the GPR; and MCLK inputs from an external clock source on the board level when clearing this bit. The SAI chapter mentions something similar in its MCLK section as well. But I can't find any clock MUX for the MCLK of SAI by selecting between the CCM and the external PAD: there is only a MUX inside the CCM. So I think you need to confirm with the IC team about this bit and the clock source of SAI MCLK. And there is a crucial problem I can imagine: Is it okay to set this bit while setting SD1_CLK PAD as one of other functions rather than SAI MCLK? -- Customers might keep your code as they also use SAI2 while using SD1_CLK PAD as a GPIO input. Nicolin