Re: [PATCH 06/16] ASoC: Intel: Skylake: Add support for Load/Unload IPCs

[Vinod Koul <vinod.koul@intel.com>]

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On Thu, Dec 03, 2015 at 12:59:14AM +0000, Mark Brown wrote:
> On Wed, Dec 02, 2015 at 10:37:02AM +0530, Vinod Koul wrote:
> > On Tue, Dec 01, 2015 at 10:58:54PM +0000, Mark Brown wrote:
> 
> > > So the multiple modules are a block of at most 255 16 bit words?  That's
> > > a bit surprising - is it really a count of the number of modules or
> > > rather the size of the block of data that's being squirted at the DSP?
> 
> > Nope, as you would think that does not make sense :)
> 
> > So we do not point to module memory here, we are sending IPC saying module
> > X, Y and Z are being loaded, data contains the module IDs only. The IDs are
> > 16 bits so sizeof(u16) and number of modules pass as arg
> 
> > The modules are transfered with Code Loader DMA which invokes this as IPC
> > after preparing DMA from Host.
> 
> > This way IPC allows us to load One or multiple modules at one shot
> 
> Can you please at least put this in the same patch as the user if not
> merge it more closely?  This is another of those abstractions that's
> really unclear just sitting by itself with no explanation.

The next patch "ASoC: Intel: Skylake: Add support for Loadable modules" does
add the actual code which uses the IPC.

I think it should be okay to merge these two in single patch to have
complete feature in one patch, i will fold these, add comments for this and
resend

Thanks
-- 
~Vinod

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