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From: Vinod Koul <vinod.koul@intel.com>
To: Naveen M <naveen.m@intel.com>
Cc: Harsha Priya <harshapriya.n@intel.com>,
	alsa-devel@alsa-project.org, broonie@kernel.org,
	subhransu.s.prusty@intel.com, pierre-louis.bossart@intel.com
Subject: Re: [PATCH] ASoC: Intel: eve: Enable mclk and ssp sclk early
Date: Mon, 18 Sep 2017 09:12:36 +0530	[thread overview]
Message-ID: <20170918034236.GH30097@localhost> (raw)
In-Reply-To: <1505012579-19568-1-git-send-email-naveen.m@intel.com>

On Sun, Sep 10, 2017 at 08:32:59AM +0530, Naveen M wrote:
> rt5663 needs mclk/sclk early to synchronize its internal clocks.
> Clocks are enabled in hw_params and disabled in platform_clk_control
> as the codec requires mclk/bclk need to turned ON before set_sysclk
> call for a successful clock synchronization.

This would be dependent on the series Subhransu posted right? If so please
do mention that

> +static int kabylake_enable_ssp_clks(struct snd_soc_card *card)
> +{
> +

we don't need the empty line here

> +	struct kbl_codec_private *priv = snd_soc_card_get_drvdata(card);
> +	int ret;
> +
> +	/* Enable MCLK */
> +	ret = clk_set_rate(priv->mclk, 24000000);
> +	if (ret < 0) {
> +		dev_err(card->dev, "Can't set rate for mclk, err: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = clk_prepare_enable(priv->mclk);
> +	if (ret < 0) {
> +		dev_err(card->dev, "Can't enable mclk, err: %d\n", ret);
> +		return ret;
> +	}
> +
> +	/* Enable SCLK */
> +	ret = clk_set_rate(priv->sclk, 3072000);

why do we need both mclk and sclk for this codec? One should be enough for
codec to sync

> +	if (ret < 0) {
> +		dev_err(card->dev, "Can't set rate for sclk, err: %d\n", ret);
> +		clk_disable_unprepare(priv->mclk);
> +		return ret;
> +	}
> +
> +	ret = clk_prepare_enable(priv->sclk);
> +	if (ret < 0) {
> +		dev_err(card->dev, "Can't enable sclk, err: %d\n", ret);
> +		clk_disable_unprepare(priv->mclk);
> +	}
> +
> +	return 0;

this looks wrong to me, shouldn't this be return ret;

> @@ -647,6 +710,7 @@ static int kabylake_audio_probe(struct platform_device *pdev)
>  {
>  	struct kbl_codec_private *ctx;
>  	struct skl_machine_pdata *pdata;
> +	int ret = 0;
>  
>  	ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_ATOMIC);
>  	if (!ctx)
> @@ -662,6 +726,34 @@ static int kabylake_audio_probe(struct platform_device *pdev)
>  		dmic_constraints = pdata->dmic_num == 2 ?
>  			&constraints_dmic_2ch : &constraints_dmic_channels;
>  
> +	ctx->mclk = devm_clk_get(&pdev->dev, "ssp1_mclk");
> +	if (IS_ERR(ctx->mclk)) {
> +		ret = PTR_ERR(ctx->mclk);
> +		if (ret == -ENOENT) {
> +			dev_info(&pdev->dev,
> +				"Failed to get ssp1_mclk, defer probe\n");

can you check this, I think driver core emits warnings as well, so do we
need it here?

> +			return -EPROBE_DEFER;
> +		}
> +
> +		dev_err(&pdev->dev, "Failed to get ssp1_mclk with err:%d\n",
> +								ret);
> +		return ret;
> +	}
> +
> +	ctx->sclk = devm_clk_get(&pdev->dev, "ssp1_sclk");
> +	if (IS_ERR(ctx->sclk)) {
> +		ret = PTR_ERR(ctx->sclk);
> +		if (ret == -ENOENT) {
> +			dev_info(&pdev->dev,
> +				"Failed to get ssp1_sclk, defer probe\n");

shouldn't the mclk ref be given back?

-- 
~Vinod

  parent reply	other threads:[~2017-09-18  3:38 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-07 14:29 [PATCH 0/6] ASoC: Intel: Skylake: Add a clk driver to enable ssp clks early Subhransu S. Prusty
2017-09-07 14:29 ` [PATCH 1/6] ASoC: Intel: Skylake: Modify skl_dsp_set_dma_control API arguments Subhransu S. Prusty
2017-10-09 10:44   ` Applied "ASoC: Intel: Skylake: Modify skl_dsp_set_dma_control API arguments" to the asoc tree Mark Brown
2017-09-07 14:29 ` [PATCH 2/6] ASoC: Intel: Skylake: Parse nhlt to populate clock information Subhransu S. Prusty
2017-09-07 14:29 ` [PATCH 3/6] ASoC: Intel: Skylake: Prepare DMA control IPC to enable/disable clock Subhransu S. Prusty
2017-09-07 14:29 ` [PATCH 4/6] ASoC: Intel: Skylake: Register clock device and ops Subhransu S. Prusty
2017-09-08  1:48   ` [alsa-devel] " Pierre-Louis Bossart
2017-09-08  3:31     ` Subhransu S. Prusty
2017-09-08  5:01       ` Subhransu S. Prusty
2017-09-08 13:41         ` Pierre-Louis Bossart
2017-09-15 12:40           ` Subhransu S. Prusty
2017-09-15 12:42             ` Subhransu S. Prusty
2017-09-07 14:29 ` [PATCH 5/6] ASoC: Intel: Skylake: Add ssp clock driver Subhransu S. Prusty
2017-09-07 16:46   ` Vinod Koul
2017-10-24 14:15     ` Stephen Boyd
2017-09-07 14:29 ` [PATCH 6/6] ASoC: Intel: kbl: Enable mclk and ssp sclk early Subhransu S. Prusty
2017-09-07 22:19   ` [alsa-devel] " Pierre-Louis Bossart
2017-09-08  3:26     ` Subhransu S. Prusty
     [not found] ` <1505012579-19568-1-git-send-email-naveen.m@intel.com>
2017-09-18  3:42   ` Vinod Koul [this message]
     [not found] ` <1505021600-20416-1-git-send-email-naveen.m@intel.com>
2017-09-18  3:47   ` [PATCH v2] ASoC: Intel: eve: " Vinod Koul

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