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From: Stephen Boyd <sboyd@codeaurora.org>
To: Vinod Koul <vinod.koul@intel.com>
Cc: "Subhransu S. Prusty" <subhransu.s.prusty@intel.com>,
	broonie@kernel.org, mturquette@baylibre.com,
	alsa-devel@alsa-project.org, tiwai@suse.de, lgirdwood@gmail.com,
	patches.audio@intel.com, linux-clk@vger.kernel.org,
	harshapriya.n@intel.com,
	Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com>
Subject: Re: [PATCH 5/6] ASoC: Intel: Skylake: Add ssp clock driver
Date: Tue, 24 Oct 2017 07:15:17 -0700	[thread overview]
Message-ID: <20171024141517.GF15990@codeaurora.org> (raw)
In-Reply-To: <20170907164642.GX3053@localhost>

On 09/07, Vinod Koul wrote:
> On Thu, Sep 07, 2017 at 07:59:24PM +0530, Subhransu S. Prusty wrote:
> > From: Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com>
> > 
> > For certain platforms it is required to start the clocks (mclk/sclk/fs)
> > before the stream start. Example: for few chrome systems, codec needs the
> > mclk/sclk to be enabled early for a successful clock synchronization and
> > for few IVI platforms, clock need to be enabled at boot and should be ON
> > always.
> > 
> > This patch creates virtual clock driver, which allows the machine driver to
> > use the clock interface to send IPCs to DSP to enable/disable the clocks.
> 
> Mark, Michael, Stephen,
> 
> So this one adds a 'virtual' clock driver for audio clocks (mclk, bclk...)
> and we have DSP configuring them.  The SW (driver) sends messages to DSP for
> controlling these clocks, that is why we decided to keep this in ASoC, do
> let us know if that is okay.
> 

I know there's a v2 and I'm replying here but this is fine from
clk perspective. I tend to think of it as a "remote" driver
instead where the clk control is done by a non-linux processor or
"remote" processor, in this case the DSP. I'll ack v2.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

  reply	other threads:[~2017-10-24 14:15 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-07 14:29 [PATCH 0/6] ASoC: Intel: Skylake: Add a clk driver to enable ssp clks early Subhransu S. Prusty
2017-09-07 14:29 ` [PATCH 1/6] ASoC: Intel: Skylake: Modify skl_dsp_set_dma_control API arguments Subhransu S. Prusty
2017-10-09 10:44   ` Applied "ASoC: Intel: Skylake: Modify skl_dsp_set_dma_control API arguments" to the asoc tree Mark Brown
2017-09-07 14:29 ` [PATCH 2/6] ASoC: Intel: Skylake: Parse nhlt to populate clock information Subhransu S. Prusty
2017-09-07 14:29 ` [PATCH 3/6] ASoC: Intel: Skylake: Prepare DMA control IPC to enable/disable clock Subhransu S. Prusty
2017-09-07 14:29 ` [PATCH 4/6] ASoC: Intel: Skylake: Register clock device and ops Subhransu S. Prusty
2017-09-08  1:48   ` [alsa-devel] " Pierre-Louis Bossart
2017-09-08  3:31     ` Subhransu S. Prusty
2017-09-08  5:01       ` Subhransu S. Prusty
2017-09-08 13:41         ` Pierre-Louis Bossart
2017-09-15 12:40           ` Subhransu S. Prusty
2017-09-15 12:42             ` Subhransu S. Prusty
2017-09-07 14:29 ` [PATCH 5/6] ASoC: Intel: Skylake: Add ssp clock driver Subhransu S. Prusty
2017-09-07 16:46   ` Vinod Koul
2017-10-24 14:15     ` Stephen Boyd [this message]
2017-09-07 14:29 ` [PATCH 6/6] ASoC: Intel: kbl: Enable mclk and ssp sclk early Subhransu S. Prusty
2017-09-07 22:19   ` [alsa-devel] " Pierre-Louis Bossart
2017-09-08  3:26     ` Subhransu S. Prusty
     [not found] ` <1505012579-19568-1-git-send-email-naveen.m@intel.com>
2017-09-18  3:42   ` [PATCH] ASoC: Intel: eve: " Vinod Koul
     [not found] ` <1505021600-20416-1-git-send-email-naveen.m@intel.com>
2017-09-18  3:47   ` [PATCH v2] " Vinod Koul

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