From: Mark Brown <broonie@kernel.org>
To: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: shengjiu.wang@nxp.com, timur@kernel.org, Xiubo.Lee@gmail.com,
festevam@gmail.com, lgirdwood@gmail.com, perex@perex.cz,
tiwai@suse.com, alsa-devel@alsa-project.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [RFC/RFT PATCH] Revert "ASoC: fsl_esai: ETDR and TX0~5 registers are non volatile"
Date: Fri, 7 Jun 2019 12:12:44 +0100 [thread overview]
Message-ID: <20190607111244.GE2456@sirena.org.uk> (raw)
In-Reply-To: <20190606230105.4385-1-nicoleotsuka@gmail.com>
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On Thu, Jun 06, 2019 at 04:01:05PM -0700, Nicolin Chen wrote:
> This reverts commit 8973112aa41b8ad956a5b47f2fe17bc2a5cf2645.
Please use subject lines matching the style for the subsystem. This
makes it easier for people to identify relevant patches.
> 1) Though ETDR and TX0~5 are not volatile but write-only registers,
> they should not be cached either. According to the definition of
> "volatile_reg", one should be put in the volatile list if it can
> not be cached.
There's no problem with caching write only registers, having a cache
allows one to do read/modify/write cycles on them and can help with
debugging. The original reason we had cache code in ASoC was for write
only devices.
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next prev parent reply other threads:[~2019-06-07 11:12 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-06 23:01 [RFC/RFT PATCH] Revert "ASoC: fsl_esai: ETDR and TX0~5 registers are non volatile" Nicolin Chen
2019-06-07 11:12 ` Mark Brown [this message]
2019-06-07 22:05 ` Nicolin Chen
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