From mboxrd@z Thu Jan 1 00:00:00 1970 From: Nicolin Chen Subject: Re: [RFC/RFT PATCH] Revert "ASoC: fsl_esai: ETDR and TX0~5 registers are non volatile" Date: Fri, 7 Jun 2019 15:05:18 -0700 Message-ID: <20190607220517.GA3824@Asurada-Nvidia.nvidia.com> References: <20190606230105.4385-1-nicoleotsuka@gmail.com> <20190607111244.GE2456@sirena.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20190607111244.GE2456@sirena.org.uk> Sender: linux-kernel-owner@vger.kernel.org To: Mark Brown Cc: shengjiu.wang@nxp.com, timur@kernel.org, Xiubo.Lee@gmail.com, festevam@gmail.com, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org List-Id: alsa-devel@alsa-project.org Hello Mark, On Fri, Jun 07, 2019 at 12:12:44PM +0100, Mark Brown wrote: > On Thu, Jun 06, 2019 at 04:01:05PM -0700, Nicolin Chen wrote: > > This reverts commit 8973112aa41b8ad956a5b47f2fe17bc2a5cf2645. > > Please use subject lines matching the style for the subsystem. This > makes it easier for people to identify relevant patches. > > > 1) Though ETDR and TX0~5 are not volatile but write-only registers, > > they should not be cached either. According to the definition of > > "volatile_reg", one should be put in the volatile list if it can > > not be cached. > > There's no problem with caching write only registers, having a cache > allows one to do read/modify/write cycles on them and can help with > debugging. The original reason we had cache code in ASoC was for write > only devices. Maybe because my paragraph doesn't state it clearly -- it's nothing wrong with regmap caching write-only registers; but it caching data registers would potentially cause dirty data or channel swap/shift. So the reason (1) here is "cannot cached" == "should be volatile". I will revise the commit message for review and fix the subject. Thank you Nicolin