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[216.228.112.22]) by smtp.gmail.com with ESMTPSA id u4sm124058pfu.177.2019.09.16.15.43.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Sep 2019 15:43:05 -0700 (PDT) Date: Mon, 16 Sep 2019 15:42:45 -0700 From: Nicolin Chen To: "S.j. Wang" Message-ID: <20190916224244.GA12789@Asurada-Nvidia.nvidia.com> References: <20190912235103.GD24937@Asurada-Nvidia.nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Cc: "alsa-devel@alsa-project.org" , "timur@kernel.org" , "Xiubo.Lee@gmail.com" , "linuxppc-dev@lists.ozlabs.org" , "tiwai@suse.com" , "lgirdwood@gmail.com" , "broonie@kernel.org" , "festevam@gmail.com" , "linux-kernel@vger.kernel.org" Subject: Re: [alsa-devel] [EXT] Re: [PATCH 2/3] ASoC: fsl_asrc: update supported sample format X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Fri, Sep 13, 2019 at 05:48:40AM +0000, S.j. Wang wrote: > Hi > > > > > On Tue, Sep 10, 2019 at 02:07:25AM +0000, S.j. Wang wrote: > > > > On Mon, Sep 09, 2019 at 06:33:20PM -0400, Shengjiu Wang wrote: > > > > > The ASRC support 24bit/16bit/8bit input width, so S20_3LE format > > > > > should not be supported, it is word width is 20bit. > > > > > > > > I thought 3LE used 24-bit physical width. And the driver assigns > > > > ASRC_WIDTH_24_BIT to "width" for all non-16bit cases, so 20-bit > > > > would go for that 24-bit slot also. I don't clearly recall if I had > > > > explicitly tested S20_3LE, but I feel it should work since I put there... > > > > > > For S20_3LE, the width is 20bit, but the ASRC only support 24bit, if > > > set the ASRMCR1n.IWD= 24bit, because the actual width is 20 bit, the > > > volume is Lower than expected, it likes 24bit data right shift 4 bit. > > > So it is not supported. > > > > Hmm..S20_3LE right-aligns 20 bits in a 24-bit slot? I thought they're left > > aligned... > > > > If this is the case...shouldn't we have the same lower-volume problem for > > all hardwares that support S20_3LE now? > > Actually some hardware/module when they do transmission from FIFO > to shift register, they can select the start bit, for example from the 20th > bit. but not all module have this capability. > > For ASRC, it haven't. IWD can only cover the data width, there is no > Other bit for slot width. Okay..let's drop the S20_3LE then. But would it be possible for you to elaborate the reasoning into the commit message also? Just for case when people ask why we remove it simply. Thanks _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org https://mailman.alsa-project.org/mailman/listinfo/alsa-devel