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[216.228.112.22]) by smtp.gmail.com with ESMTPSA id v12sm152839pgr.31.2019.09.16.16.11.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Sep 2019 16:11:34 -0700 (PDT) Date: Mon, 16 Sep 2019 16:11:15 -0700 From: Nicolin Chen To: Daniel Baluta Message-ID: <20190916231115.GD12789@Asurada-Nvidia.nvidia.com> References: <20190913192807.8423-1-daniel.baluta@nxp.com> <20190913192807.8423-4-daniel.baluta@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190913192807.8423-4-daniel.baluta@nxp.com> User-Agent: Mutt/1.9.4 (2018-02-28) Cc: alsa-devel@alsa-project.org, timur@kernel.org, Xiubo.Lee@gmail.com, linux-kernel@vger.kernel.org, tiwai@suse.com, lgirdwood@gmail.com, broonie@kernel.org, NXP Linux Team , festevam@gmail.com Subject: Re: [alsa-devel] [PATCH v2 3/3] ASoC: fsl_sai: Fix TCSR.TE/RCSR.RE in synchronous mode X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Hello Daniel, On Fri, Sep 13, 2019 at 10:28:07PM +0300, Daniel Baluta wrote: > The SAI transmitter and receiver can be configured to operate with > synchronous bit clock and frame sync. > > When Tx is synchronous with receiver RCSR.RE should be set in playback > to enable the receiver which provides bit clock and frame sync. > > When Rx is synchronous with transmitter TCSR.TE should be set in record > to enable the transmitter which provides bit clock and frame sync. I don't quite get what this patch fixes....can you explain? > @@ -539,8 +539,8 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, > sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); > > /* > - * It is recommended that the transmitter is the last enabled > - * and the first disabled. This is copied from iMX6SX Reference Manual, IIRC...And I just took a look at iMX8DXP/QXP RM: it has the exact same statement in "16.16.3.3.1 Synchronous mode" section. > + * it is recommended that the asynchronous block to be the last enabled > + * and the first disabled So... why are we changing to this? Any update/explain? Thank you _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org https://mailman.alsa-project.org/mailman/listinfo/alsa-devel