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[216.228.112.21]) by smtp.gmail.com with ESMTPSA id c14sm2839648pfj.82.2020.07.15.13.47.02 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 15 Jul 2020 13:47:02 -0700 (PDT) Date: Wed, 15 Jul 2020 13:46:38 -0700 From: Nicolin Chen To: Arnaud Ferraris Subject: Re: [PATCH 0/4] ASoC: fsl_asrc: allow selecting arbitrary clocks Message-ID: <20200715204636.GA14539@Asurada-Nvidia> References: <20200702142235.235869-1-arnaud.ferraris@collabora.com> <20200702184226.GA23935@Asurada-Nvidia> <3f39a0bb-a766-f646-28b3-a51cf9983c6b@collabora.com> <3fea8912-63df-ff27-0c29-6284a85107ab@collabora.com> <20200714201544.GA10501@Asurada-Nvidia> <20200714202753.GM4900@sirena.org.uk> <20200714205050.GB10501@Asurada-Nvidia> <20200715140519.GH5431@sirena.org.uk> <0a56326b-27a9-d9f4-3923-8773963d7548@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <0a56326b-27a9-d9f4-3923-8773963d7548@collabora.com> User-Agent: Mutt/1.9.4 (2018-02-28) Cc: alsa-devel@alsa-project.org, Timur Tabi , Xiubo Li , Liam Girdwood , Takashi Iwai , Rob Herring , linux-kernel@vger.kernel.org, Mark Brown , kernel@collabora.com, Fabio Estevam X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Wed, Jul 15, 2020 at 06:18:38PM +0200, Arnaud Ferraris wrote: > Hi, > > Le 15/07/2020 à 16:05, Mark Brown a écrit : > > On Tue, Jul 14, 2020 at 01:50:50PM -0700, Nicolin Chen wrote: > > Anything wrong with ASRC selecting SSI1 clock for both cases? The > > driver calculates the divisors based on the given clock rate, so > > the final internal rate should be the same. If there's a problem, > > I feel that's a separate bug. > > Calculations are indeed good, but then the clock selection setting in > the ASRCSR register would also use SSI1 as the input clock, which > doesn't work in our case. Could you please elaborate why it doesn't work?