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d="scan'208";a="460699627" Received: from bard-ubuntu.sh.intel.com ([10.239.13.33]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jul 2020 20:04:02 -0700 From: Bard Liao To: alsa-devel@alsa-project.org, vkoul@kernel.org Subject: [PATCH v2 1/9] soundwire: intel: reuse code for wait loops to set/clear bits Date: Thu, 16 Jul 2020 23:09:39 +0800 Message-Id: <20200716150947.22119-2-yung-chuan.liao@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200716150947.22119-1-yung-chuan.liao@linux.intel.com> References: <20200716150947.22119-1-yung-chuan.liao@linux.intel.com> Cc: pierre-louis.bossart@linux.intel.com, vinod.koul@linaro.org, tiwai@suse.de, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, ranjani.sridharan@linux.intel.com, hui.wang@canonical.com, broonie@kernel.org, srinivas.kandagatla@linaro.org, jank@cadence.com, mengdong.lin@intel.com, slawomir.blauciak@intel.com, sanyog.r.kale@intel.com, rander.wang@linux.intel.com, bard.liao@intel.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Pierre-Louis Bossart Refactor code and use same routines on set/clear Signed-off-by: Pierre-Louis Bossart Signed-off-by: Bard Liao --- drivers/soundwire/intel.c | 45 +++++++++++++++++---------------------- 1 file changed, 19 insertions(+), 26 deletions(-) diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c index 7a65414e5714..8c7ae07c0fe1 100644 --- a/drivers/soundwire/intel.c +++ b/drivers/soundwire/intel.c @@ -123,40 +123,33 @@ static inline void intel_writew(void __iomem *base, int offset, u16 value) writew(value, base + offset); } +static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target) +{ + int timeout = 10; + u32 reg_read; + + do { + reg_read = readl(base + offset); + if ((reg_read & mask) == target) + return 0; + + timeout--; + usleep_range(50, 100); + } while (timeout != 0); + + return -EAGAIN; +} + static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask) { - int timeout = 10; - u32 reg_read; - writel(value, base + offset); - do { - reg_read = readl(base + offset); - if (!(reg_read & mask)) - return 0; - - timeout--; - udelay(50); - } while (timeout != 0); - - return -EAGAIN; + return intel_wait_bit(base, offset, mask, 0); } static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask) { - int timeout = 10; - u32 reg_read; - writel(value, base + offset); - do { - reg_read = readl(base + offset); - if (reg_read & mask) - return 0; - - timeout--; - udelay(50); - } while (timeout != 0); - - return -EAGAIN; + return intel_wait_bit(base, offset, mask, mask); } /* -- 2.17.1