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[216.228.112.21]) by smtp.gmail.com with ESMTPSA id u16sm1295001pfn.52.2020.07.22.22.46.39 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Jul 2020 22:46:40 -0700 (PDT) Date: Wed, 22 Jul 2020 22:46:07 -0700 From: Nicolin Chen To: Arnaud Ferraris Subject: Re: [PATCH 0/4] ASoC: fsl_asrc: allow selecting arbitrary clocks Message-ID: <20200723054604.GC5476@Asurada-Nvidia> References: <20200702142235.235869-1-arnaud.ferraris@collabora.com> <20200702184226.GA23935@Asurada-Nvidia> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org, Timur Tabi , Xiubo Li , linux-kernel@vger.kernel.org, Takashi Iwai , Liam Girdwood , Rob Herring , Mark Brown , kernel@collabora.com, Fabio Estevam X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Fri, Jul 17, 2020 at 01:16:42PM +0200, Arnaud Ferraris wrote: > Hi Nic, > > Le 02/07/2020 à 20:42, Nicolin Chen a écrit : > > Hi Arnaud, > > > > On Thu, Jul 02, 2020 at 04:22:31PM +0200, Arnaud Ferraris wrote: > >> The current ASRC driver hardcodes the input and output clocks used for > >> sample rate conversions. In order to allow greater flexibility and to > >> cover more use cases, it would be preferable to select the clocks using > >> device-tree properties. > > > > We recent just merged a new change that auto-selecting internal > > clocks based on sample rates as the first option -- ideal ratio > > mode is the fallback mode now. Please refer to: > > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20200702&id=d0250cf4f2abfbea64ed247230f08f5ae23979f0 > > While working on fixing the automatic clock selection (see my v3), I > came across another potential issue, which would be better explained > with an example: > - Input has sample rate 8kHz and uses clock SSI1 with rate 512kHz > - Output has sample rate 16kHz and uses clock SSI2 with rate 1024kHz > > Let's say my v3 patch is merged, then the selected input clock will be > SSI1, while the selected output clock will be SSI2. In that case, it's > all good, as the driver will calculate the dividers right. > > Now, suppose a similar board has the input wired to SSI2 and output to > SSI1, meaning we're now in the following case: > - Input has sample rate 8kHz and uses clock SSI2 with rate 512kHz > - Output has sample rate 16kHz and uses clock SSI1 with rate 1024kHz > (the same result is achieved during capture with the initial example > setup, as input and output properties are then swapped) > > In that case, the selected clocks will still be SSI1 for input (just > because it appears first in the clock table), and SSI2 for output, > meaning the calculated dividers will be: > - input: 512 / 16 => 32 (should be 64) > - output: 1024 / 8 => 128 (should be 64 here too) I don't get the 32, 128 and 64 parts. Would you please to elaborate a bit? What you said sounds to me like the driver calculates wrong dividers?