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d="scan'208";a="328862565" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.40]) by orsmga008.jf.intel.com with ESMTP; 25 Aug 2020 06:23:07 -0700 Received: from andy by smile with local (Exim 4.94) (envelope-from ) id 1kAYun-00BKcV-3z; Tue, 25 Aug 2020 16:23:05 +0300 Date: Tue, 25 Aug 2020 16:23:05 +0300 From: Andy Shevchenko To: Cezary Rojewski Subject: Re: [PATCH v4 02/13] ASoC: Intel: catpt: Define DSP operations Message-ID: <20200825132305.GJ1891694@smile.fi.intel.com> References: <20200812205753.29115-1-cezary.rojewski@intel.com> <20200812205753.29115-3-cezary.rojewski@intel.com> <20200813185129.GB1891694@smile.fi.intel.com> <946fdd80-c89d-ee1b-6eef-e752318b55a6@intel.com> <237f2343-fd57-8ebf-b8f2-8c2cf5c3c745@intel.com> <20200820090055.GT1891694@smile.fi.intel.com> <20200825131615.GG1891694@smile.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200825131615.GG1891694@smile.fi.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Cc: pierre-louis.bossart@linux.intel.com, alsa-devel@alsa-project.org, filip.kaczmarski@intel.com, harshapriya.n@intel.com, marcin.barlik@intel.com, zwisler@google.com, lgirdwood@gmail.com, tiwai@suse.com, filip.proborszcz@intel.com, broonie@kernel.org, amadeuszx.slawinski@linux.intel.com, michal.wasko@intel.com, cujomalainey@chromium.org, krzysztof.hejmowski@intel.com, ppapierkowski@habana.ai, vamshi.krishna.gopal@intel.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Tue, Aug 25, 2020 at 04:16:15PM +0300, Andy Shevchenko wrote: > On Mon, Aug 24, 2020 at 06:33:17PM +0200, Cezary Rojewski wrote: > > On 2020-08-20 11:00 AM, Andy Shevchenko wrote: ... > > Another question though: PCI_PM_CTRL. In order for me to make use of this, > > "pm_cap" member would have to be declared for my device. As this is no > > struct pci_dev, catpt has currently no separate member for that purpose. I > > don't believe you want me to add that field into struct's declaration. > > Second option is to define constant for pm_cap offset aka 0x80 within > > registers.h and then do the operations as follows: > > catpt_updatel_pci(cdev, CATPT_PM_CAP + PCI_PM_CTRL, ...) > > > However, in such case I won't be able to make use of current version of > > _updatel_pci() as definition of that macro allows me to skip prefix and type > > implicitly - PMCS (the rest is appended automatically). > > Maybe let's leave it within registers.h altogether so I can actually keep > > using said macro? > > Basically what you do with accessing PCI configuration space via these methods > (catpt_update_pci(), etc) is something repetitive / similar to what xHCI DbC > support code does. I recommend to spend some time to look for similarities here > (catpt) and there (PCI core, xHCI DbC, etc) and, if we were lucky, derive > common helpers for traverse the capability list in more generalized way. Throwing the idea loud: perhaps we may have something like regmap-pci.c to access PCI configuration space and make regmap API to take care of which IO accessors (and locking) will be used. -- With Best Regards, Andy Shevchenko