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[216.228.112.22]) by smtp.gmail.com with ESMTPSA id gd14sm4050934pjb.0.2020.09.16.18.54.00 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Sep 2020 18:54:00 -0700 (PDT) Date: Wed, 16 Sep 2020 18:50:49 -0700 From: Nicolin Chen To: Shengjiu Wang Subject: Re: [PATCH 3/3] ASoC: fsl_sai: Set MCLK input or output direction Message-ID: <20200917015048.GD22566@Asurada-Nvidia> References: <1600251387-1863-1-git-send-email-shengjiu.wang@nxp.com> <1600251387-1863-4-git-send-email-shengjiu.wang@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1600251387-1863-4-git-send-email-shengjiu.wang@nxp.com> User-Agent: Mutt/1.9.4 (2018-02-28) Cc: alsa-devel@alsa-project.org, timur@kernel.org, Xiubo.Lee@gmail.com, lgirdwood@gmail.com, linuxppc-dev@lists.ozlabs.org, tiwai@suse.com, broonie@kernel.org, festevam@gmail.com, linux-kernel@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Wed, Sep 16, 2020 at 06:16:27PM +0800, Shengjiu Wang wrote: > SAI support select MCLK direction with version.major > 3 > and version.minor > 1, the default direction is input, > set it to be output according to DT property. > > Signed-off-by: Shengjiu Wang Acked-by: Nicolin Chen > --- > sound/soc/fsl/fsl_sai.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c > index 738b4dda7847..5117c1cd5682 100644 > --- a/sound/soc/fsl/fsl_sai.c > +++ b/sound/soc/fsl/fsl_sai.c > @@ -1117,6 +1117,13 @@ static int fsl_sai_probe(struct platform_device *pdev) > if (ret < 0) > dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret); > > + /* Select MCLK direction */ > + if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && > + sai->verid.major >= 3 && sai->verid.minor >= 1) { > + regmap_update_bits(sai->regmap, FSL_SAI_MCTL, > + FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); > + } > + > pm_runtime_enable(&pdev->dev); > regcache_cache_only(sai->regmap, true); > > -- > 2.27.0 >