From: Cezary Rojewski <cezary.rojewski@intel.com>
To: alsa-devel@alsa-project.org
Cc: Cezary Rojewski <cezary.rojewski@intel.com>,
rad@semihalf.com, upstream@semihalf.com, harshapriya.n@intel.com,
tiwai@suse.com, pierre-louis.bossart@linux.intel.com,
hdegoede@redhat.com, broonie@kernel.org,
ranjani.sridharan@linux.intel.com,
amadeuszx.slawinski@linux.intel.com, cujomalainey@chromium.org,
lma@semihalf.com
Subject: [PATCH v4 01/17] ALSA: hda: Add helper macros for DSP capable devices
Date: Wed, 9 Mar 2022 21:40:13 +0100 [thread overview]
Message-ID: <20220309204029.89040-2-cezary.rojewski@intel.com> (raw)
In-Reply-To: <20220309204029.89040-1-cezary.rojewski@intel.com>
HDAudio drivers make heavy use of I/O operations. Declare a range of
update, read and write helpers similar to those available for HDAudio
legacy driver. These macros are used by AVS driver to improve code
readability.
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
---
include/sound/hdaudio.h | 2 ++
include/sound/hdaudio_ext.h | 50 +++++++++++++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h
index 6a90ce405e60..69907260b9ce 100644
--- a/include/sound/hdaudio.h
+++ b/include/sound/hdaudio.h
@@ -448,6 +448,8 @@ static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr)
#define snd_hdac_reg_writel(bus, addr, val) writel(val, addr)
#define snd_hdac_reg_readl(bus, addr) readl(addr)
+#define snd_hdac_reg_writeq(bus, addr, val) writeq(val, addr)
+#define snd_hdac_reg_readq(bus, addr) readq(addr)
/*
* macros for easy use
diff --git a/include/sound/hdaudio_ext.h b/include/sound/hdaudio_ext.h
index b0c8e4936168..d26234f9ee46 100644
--- a/include/sound/hdaudio_ext.h
+++ b/include/sound/hdaudio_ext.h
@@ -2,6 +2,8 @@
#ifndef __SOUND_HDAUDIO_EXT_H
#define __SOUND_HDAUDIO_EXT_H
+#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/iopoll.h>
#include <sound/hdaudio.h>
int snd_hdac_ext_bus_init(struct hdac_bus *bus, struct device *dev,
@@ -144,6 +146,54 @@ void snd_hdac_ext_bus_link_power(struct hdac_device *codec, bool enable);
writew(((readw(addr + reg) & ~(mask)) | (val)), \
addr + reg)
+#define snd_hdac_adsp_writeb(chip, reg, value) \
+ snd_hdac_reg_writeb(chip, (chip)->dsp_ba + (reg), value)
+#define snd_hdac_adsp_readb(chip, reg) \
+ snd_hdac_reg_readb(chip, (chip)->dsp_ba + (reg))
+#define snd_hdac_adsp_writew(chip, reg, value) \
+ snd_hdac_reg_writew(chip, (chip)->dsp_ba + (reg), value)
+#define snd_hdac_adsp_readw(chip, reg) \
+ snd_hdac_reg_readw(chip, (chip)->dsp_ba + (reg))
+#define snd_hdac_adsp_writel(chip, reg, value) \
+ snd_hdac_reg_writel(chip, (chip)->dsp_ba + (reg), value)
+#define snd_hdac_adsp_readl(chip, reg) \
+ snd_hdac_reg_readl(chip, (chip)->dsp_ba + (reg))
+#define snd_hdac_adsp_writeq(chip, reg, value) \
+ snd_hdac_reg_writeq(chip, (chip)->dsp_ba + (reg), value)
+#define snd_hdac_adsp_readq(chip, reg) \
+ snd_hdac_reg_readq(chip, (chip)->dsp_ba + (reg))
+
+#define snd_hdac_adsp_updateb(chip, reg, mask, val) \
+ snd_hdac_adsp_writeb(chip, reg, \
+ (snd_hdac_adsp_readb(chip, reg) & ~(mask)) | (val))
+#define snd_hdac_adsp_updatew(chip, reg, mask, val) \
+ snd_hdac_adsp_writew(chip, reg, \
+ (snd_hdac_adsp_readw(chip, reg) & ~(mask)) | (val))
+#define snd_hdac_adsp_updatel(chip, reg, mask, val) \
+ snd_hdac_adsp_writel(chip, reg, \
+ (snd_hdac_adsp_readl(chip, reg) & ~(mask)) | (val))
+#define snd_hdac_adsp_updateq(chip, reg, mask, val) \
+ snd_hdac_adsp_writeq(chip, reg, \
+ (snd_hdac_adsp_readq(chip, reg) & ~(mask)) | (val))
+
+#define snd_hdac_adsp_readb_poll(chip, reg, val, cond, delay_us, timeout_us) \
+ readb_poll_timeout((chip)->dsp_ba + (reg), val, cond, \
+ delay_us, timeout_us)
+#define snd_hdac_adsp_readw_poll(chip, reg, val, cond, delay_us, timeout_us) \
+ readw_poll_timeout((chip)->dsp_ba + (reg), val, cond, \
+ delay_us, timeout_us)
+#define snd_hdac_adsp_readl_poll(chip, reg, val, cond, delay_us, timeout_us) \
+ readl_poll_timeout((chip)->dsp_ba + (reg), val, cond, \
+ delay_us, timeout_us)
+#define snd_hdac_adsp_readq_poll(chip, reg, val, cond, delay_us, timeout_us) \
+ readq_poll_timeout((chip)->dsp_ba + (reg), val, cond, \
+ delay_us, timeout_us)
+#define snd_hdac_stream_readb_poll(strm, reg, val, cond, delay_us, timeout_us) \
+ readb_poll_timeout((strm)->sd_addr + AZX_REG_ ## reg, val, cond, \
+ delay_us, timeout_us)
+#define snd_hdac_stream_readl_poll(strm, reg, val, cond, delay_us, timeout_us) \
+ readl_poll_timeout((strm)->sd_addr + AZX_REG_ ## reg, val, cond, \
+ delay_us, timeout_us)
struct hdac_ext_device;
--
2.25.1
next prev parent reply other threads:[~2022-03-09 20:31 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-09 20:40 [PATCH v4 00/17] ASoC: Intel: AVS - Audio DSP for cAVS Cezary Rojewski
2022-03-09 20:40 ` Cezary Rojewski [this message]
2022-03-10 13:30 ` [PATCH v4 01/17] ALSA: hda: Add helper macros for DSP capable devices Takashi Iwai
2022-03-09 20:40 ` [PATCH v4 02/17] ASoC: Export DAI register and widget ctor and dctor functions Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 03/17] ASoC: Intel: Introduce AVS driver Cezary Rojewski
2022-03-09 21:58 ` Pierre-Louis Bossart
2022-03-11 15:32 ` Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 04/17] ASoC: Intel: avs: Inter process communication Cezary Rojewski
2022-03-09 22:10 ` Pierre-Louis Bossart
2022-03-11 15:40 ` Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 05/17] ASoC: Intel: avs: Add code loading requests Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 06/17] ASoC: Intel: avs: Add pipeline management requests Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 07/17] ASoC: Intel: avs: Add module " Cezary Rojewski
2022-03-09 22:16 ` Pierre-Louis Bossart
2022-03-11 15:40 ` Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 08/17] ASoC: Intel: avs: Add power " Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 09/17] ASoC: Intel: avs: Add ROM requests Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 10/17] ASoC: Intel: avs: Add basefw runtime-parameter requests Cezary Rojewski
2022-03-09 22:20 ` Pierre-Louis Bossart
2022-03-09 20:40 ` [PATCH v4 11/17] ASoC: Intel: avs: Firmware resources management utilities Cezary Rojewski
2022-03-09 22:36 ` Pierre-Louis Bossart
2022-03-10 17:11 ` Cezary Rojewski
2022-03-11 12:10 ` Mark Brown
2022-03-11 15:28 ` Cezary Rojewski
2022-03-11 15:46 ` Cezary Rojewski
2022-03-11 15:59 ` Pierre-Louis Bossart
2022-03-11 17:20 ` Cezary Rojewski
2022-03-11 20:30 ` Pierre-Louis Bossart
2022-03-14 17:59 ` Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 12/17] ASoC: Intel: avs: Declare module configuration types Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 13/17] ASoC: Intel: avs: Dynamic firmware resources management Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 14/17] ASoC: Intel: avs: General code loading flow Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 15/17] ASoC: Intel: avs: Implement CLDMA transfer Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 16/17] ASoC: Intel: avs: Code loading over CLDMA Cezary Rojewski
2022-03-09 20:40 ` [PATCH v4 17/17] ASoC: Intel: avs: Code loading over HDA Cezary Rojewski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220309204029.89040-2-cezary.rojewski@intel.com \
--to=cezary.rojewski@intel.com \
--cc=alsa-devel@alsa-project.org \
--cc=amadeuszx.slawinski@linux.intel.com \
--cc=broonie@kernel.org \
--cc=cujomalainey@chromium.org \
--cc=harshapriya.n@intel.com \
--cc=hdegoede@redhat.com \
--cc=lma@semihalf.com \
--cc=pierre-louis.bossart@linux.intel.com \
--cc=rad@semihalf.com \
--cc=ranjani.sridharan@linux.intel.com \
--cc=tiwai@suse.com \
--cc=upstream@semihalf.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).