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From: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
To: lgirdwood@gmail.com, broonie@kernel.org
Cc: alsa-devel@alsa-project.org, rander.wang@intel.com,
	pierre-louis.bossart@linux.intel.com,
	kai.vehmanen@linux.intel.com, ranjani.sridharan@linux.intel.com
Subject: [PATCH 0/4] ASoC: SOF: Intel: Harden the IPC4 low level sequencing
Date: Tue, 18 Oct 2022 15:40:04 +0300	[thread overview]
Message-ID: <20221018124008.6846-1-peter.ujfalusi@linux.intel.com> (raw)

Hi,

The IPC4 use of doorbell registers leaves some corner cases not well defined
and the 'correct sequences' are subjective in a sense.
The DSP doorbell registers are used as separate and independent channels and
the sequences for host -> DSP -> host (reply) can be racy.

For example:
The ACKing of a received message can happen before the firmware sends the reply
or it can as well happen after the reply has been sent and received by the host.
Both can be considered 'correct sequences' but they need different handling.

This series will allow the kernel to service any interpretation of the
sequencing on the firmware side.

Regards,
Peter
---
Peter Ujfalusi (4):
  ASoC: SOF: ipc4: Log the tx message before sending it
  ASoC: SOF: Intel: ipc4: Read the interrupt reason registers at the
    same time
  ASoC: SOF: Intel: ipc4: Wait for channel to be free before sending a
    message
  ASoC: SOF: Intel: ipc4: Ack a received reply or notification
    separately

 sound/soc/sof/intel/cnl.c     | 26 ++++++++++++++++++++++----
 sound/soc/sof/intel/hda-ipc.c | 27 +++++++++++++++++++++++----
 sound/soc/sof/intel/hda.c     | 11 +++++++++++
 sound/soc/sof/intel/hda.h     |  9 +++++++++
 sound/soc/sof/intel/mtl.c     | 24 +++++++++++++++++++++---
 sound/soc/sof/ipc4.c          |  4 ++--
 6 files changed, 88 insertions(+), 13 deletions(-)

-- 
2.38.0


             reply	other threads:[~2022-10-18 12:40 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-18 12:40 Peter Ujfalusi [this message]
2022-10-18 12:40 ` [PATCH 1/4] ASoC: SOF: ipc4: Log the tx message before sending it Peter Ujfalusi
2022-10-18 12:40 ` [PATCH 2/4] ASoC: SOF: Intel: ipc4: Read the interrupt reason registers at the same time Peter Ujfalusi
2022-10-18 12:40 ` [PATCH 3/4] ASoC: SOF: Intel: ipc4: Wait for channel to be free before sending a message Peter Ujfalusi
2022-10-18 12:40 ` [PATCH 4/4] ASoC: SOF: Intel: ipc4: Ack a received reply or notification separately Peter Ujfalusi
2022-10-19 14:18 ` [PATCH 0/4] ASoC: SOF: Intel: Harden the IPC4 low level sequencing Mark Brown

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