From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A75CC4332F for ; Mon, 28 Nov 2022 17:42:47 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 3F0891687; Mon, 28 Nov 2022 18:41:55 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 3F0891687 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1669657365; bh=DPPczfweauoHm+8fcnAinxuupRv+3HXZOb4CpCady1A=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Xh7V5ClUx9w0wxdBzudZKLPo9fqR7R+NW0XHn1RrmD45hHWg06JkglOSrmdkKM+JK ODmi2jXv40q5UDvMvAs/u9uXa2LVIRZBqG0pSWoe9Fybc2eCUjfhgHBWFxXZAkyg06 RI6+Gjx3sflBvWVBZMq3Fp64isrIyhDeCZvueR3E= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 6CC73F8020D; Mon, 28 Nov 2022 18:41:48 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id CEFCEF8024C; Mon, 28 Nov 2022 18:41:47 +0100 (CET) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id D07F3F80166 for ; Mon, 28 Nov 2022 18:41:41 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz D07F3F80166 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZCRNOGpy" Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 07DDDB80E56; Mon, 28 Nov 2022 17:41:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 797D7C433D7; Mon, 28 Nov 2022 17:41:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1669657299; bh=DPPczfweauoHm+8fcnAinxuupRv+3HXZOb4CpCady1A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZCRNOGpyReN81FmMDiMlTu2uCIgruXZdo/TCZ+ycUQfuKamS1LfUAkOL8x/n5hD5V 2eIh8xkBYjE9Jinly8Dfi2GIUje+5ECK3CpYnsGkxPeRV/PpXWiwDrLtgvMLvdp0FE Gp95aJm1xov5zzlZOqmCExFtXvBoRLB5/NFxinvoL47Rlf4LQdqmQDLBBEZFErRGC7 HNL8j49R7hzYWpppIzaZWNbWxXTKobrY88UrZsQyQd33PyfE/ODPI+93RJdGHIaQmw 5KuY39CPvywP41w/jUqfMgvjoUqS5iGRjcS52fVO25xoZ1eEZ73czr1HCTfMFEkIVc VKJQDY17WnJhQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH AUTOSEL 5.10 08/19] ASoC: wm8962: Wait for updated value of WM8962_CLOCKING1 register Date: Mon, 28 Nov 2022 12:41:08 -0500 Message-Id: <20221128174120.1442235-8-sashal@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221128174120.1442235-1-sashal@kernel.org> References: <20221128174120.1442235-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Cc: Sasha Levin , alsa-devel@alsa-project.org, Charles Keepax , patches@opensource.cirrus.com, tiwai@suse.com, lgirdwood@gmail.com, chi.minghao@zte.com.cn, Mark Brown , Chancel Liu , steve@sk2.org, aford173@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Chancel Liu [ Upstream commit 3ca507bf99611c82dafced73e921c1b10ee12869 ] DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate correct frequency of LRCLK and BCLK. Sometimes the read-only value can't be updated timely after enabling SYSCLK. This results in wrong calculation values. Delay is introduced here to wait for newest value from register. The time of the delay should be at least 500~1000us according to test. Signed-off-by: Chancel Liu Acked-by: Charles Keepax Link: https://lore.kernel.org/r/20221109121354.123958-1-chancel.liu@nxp.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/codecs/wm8962.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index 21574447650c..57aeded978c2 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -2489,6 +2489,14 @@ static void wm8962_configure_bclk(struct snd_soc_component *component) snd_soc_component_update_bits(component, WM8962_CLOCKING2, WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA); + /* DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate + * correct frequency of LRCLK and BCLK. Sometimes the read-only value + * can't be updated timely after enabling SYSCLK. This results in wrong + * calculation values. Delay is introduced here to wait for newest + * value from register. The time of the delay should be at least + * 500~1000us according to test. + */ + usleep_range(500, 1000); dspclk = snd_soc_component_read(component, WM8962_CLOCKING1); if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON) -- 2.35.1