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Sun, 26 Feb 2023 09:48:38 -0800 (PST) Received: (nullmailer pid 84297 invoked by uid 1000); Sun, 26 Feb 2023 17:48:33 -0000 Date: Sun, 26 Feb 2023 11:48:33 -0600 From: Rob Herring To: Herve Codina Subject: Re: [PATCH v6 01/10] dt-bindings: soc: fsl: cpm_qe: Add TSA controller Message-ID: <20230226174833.GA76710-robh@kernel.org> References: <20230217145645.1768659-1-herve.codina@bootlin.com> <20230217145645.1768659-2-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230217145645.1768659-2-herve.codina@bootlin.com> Message-ID-Hash: VISD46ACW34GZZA6Z7MUNU2M6EH7Z2JY X-Message-ID-Hash: VISD46ACW34GZZA6Z7MUNU2M6EH7Z2JY X-MailFrom: robherring2@gmail.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: Li Yang , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Christophe Leroy , Michael Ellerman , Nicholas Piggin , Qiang Zhao , Takashi Iwai , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: On Fri, Feb 17, 2023 at 03:56:36PM +0100, Herve Codina wrote: > Add support for the time slot assigner (TSA) > available in some PowerQUICC SoC such as MPC885 > or MPC866. > > Signed-off-by: Herve Codina > --- > .../bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml | 215 ++++++++++++++++++ > include/dt-bindings/soc/cpm1-fsl,tsa.h | 13 ++ > 2 files changed, 228 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml > create mode 100644 include/dt-bindings/soc/cpm1-fsl,tsa.h > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml > new file mode 100644 > index 000000000000..332e902bcc21 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml > @@ -0,0 +1,215 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC CPM Time-slot assigner (TSA) controller > + > +maintainers: > + - Herve Codina > + > +description: > + The TSA is the time-slot assigner that can be found on some PowerQUICC SoC. > + Its purpose is to route some TDM time-slots to other internal serial > + controllers. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc885-tsa > + - fsl,mpc866-tsa > + - const: fsl,cpm1-tsa > + > + reg: > + items: > + - description: SI (Serial Interface) register base > + - description: SI RAM base > + > + reg-names: > + items: > + - const: si_regs > + - const: si_ram > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#fsl,serial-cells': #foo-cells is for when there are differing foo providers which need different number of cells. That's not the case here. > + $ref: /schemas/types.yaml#/definitions/uint32 > + const: 1 > + description: > + TSA consumers that use a phandle to TSA need to pass the serial identifier > + with this phandle (defined in dt-bindings/soc/fsl,tsa.h). > + For instance "fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>;".