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dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=qNltURwB Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 6C33661D5A; Thu, 9 May 2024 17:14:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D799FC116B1; Thu, 9 May 2024 17:14:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715274878; bh=YwUKTYOpoxA/NOjHV7A/q7cg5e41+QOvCr4wGh3um4g=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=qNltURwBHZ0ugcWbLrUYJc6RkDUcNQgiYSfZKjEwL9+mHhuhW146bkl+HHiyqOY7D wNNuItMLZg9XcI1JEb6/M6vYSge5p3d/Jqj/OmYtbmVYnvKDIu/qETs5sRmCps6IOQ 4LZSSh8xcEqDzkYGMQlizUe3dBHJGeJ27fyMc2GPvTmQUB2fR1FDljGOCifTUgm44z tODVfJsI9WuQ5oCQ1S/mdwWcfvfMNNaHEiYnNaps8KLZaGtfuR9Xjg2wUSON1ihOC1 qDjHDw8Jt0BWhP/UqDK3LVzv0+Cy99DGUte0fmFAja8ZXPpS+oNlfndpyWeqf3uBUo 7ppc6G/TeWG3A== Date: Thu, 9 May 2024 18:14:32 +0100 From: Conor Dooley To: Shengjiu Wang Cc: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shengjiu.wang@gmail.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xiubo.Lee@gmail.com, festevam@gmail.com, nicoleotsuka@gmail.com, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 2/4] ASoC: dt-bindings: fsl,xcvr: Add two PLL clock sources Message-ID: <20240509-repurpose-dumping-156b57c25960@spud> References: <1715223460-32662-1-git-send-email-shengjiu.wang@nxp.com> <1715223460-32662-3-git-send-email-shengjiu.wang@nxp.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="9OB7iJL8uyGYmSbm" Content-Disposition: inline In-Reply-To: <1715223460-32662-3-git-send-email-shengjiu.wang@nxp.com> Message-ID-Hash: 3HTHME76Y566YDI4WL4Y2QJB6O2HAIK5 X-Message-ID-Hash: 3HTHME76Y566YDI4WL4Y2QJB6O2HAIK5 X-MailFrom: conor@kernel.org X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.9 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: --9OB7iJL8uyGYmSbm Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, May 09, 2024 at 10:57:38AM +0800, Shengjiu Wang wrote: > Add two PLL clock sources, they are the parent clocks of the root clock > one is for 8kHz series rates, named as 'pll8k', another one is for > 11kHz series rates, named as 'pll11k'. They are optional clocks, > if there are such clocks, then the driver can switch between them to > support more accurate sample rates. >=20 > As 'pll8k' and 'pll11k' are optional, then add 'minItems: 4' for > clocks and clock-names properties. Despite the detail given here in the commit message, the series this is appearing in and one of the driver patches makes me a bit "suspicious" of this patch. Are these newly added clocks available on all devices, or just on the imx95, or? Thanks, Conor. >=20 > Signed-off-by: Shengjiu Wang > --- > Documentation/devicetree/bindings/sound/fsl,xcvr.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/sound/fsl,xcvr.yaml b/Docu= mentation/devicetree/bindings/sound/fsl,xcvr.yaml > index 1c74a32def09..c4660faed404 100644 > --- a/Documentation/devicetree/bindings/sound/fsl,xcvr.yaml > +++ b/Documentation/devicetree/bindings/sound/fsl,xcvr.yaml > @@ -50,6 +50,9 @@ properties: > - description: PHY clock > - description: SPBA clock > - description: PLL clock > + - description: PLL clock source for 8kHz series > + - description: PLL clock source for 11kHz series > + minItems: 4 > =20 > clock-names: > items: > @@ -57,6 +60,9 @@ properties: > - const: phy > - const: spba > - const: pll_ipg > + - const: pll8k > + - const: pll11k > + minItems: 4 > =20 > dmas: > items: > --=20 > 2.34.1 >=20 --9OB7iJL8uyGYmSbm Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZj0EeAAKCRB4tDGHoIJi 0kPzAP43Zn5AesCX1kKOSIjtrW5Vpt8hIHrIlOUZhE9kMqS8CgD+MljoXShCv6Tw G/iLAeB3RppsSsV+7vuOr03Tr0FXKAw= =oPv2 -----END PGP SIGNATURE----- --9OB7iJL8uyGYmSbm--