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Sun, 10 Dec 2023 19:44:21 -0800 (PST) Received: from [192.168.2.107] ([79.115.63.75]) by smtp.gmail.com with ESMTPSA id w2-20020a50d782000000b0054cceab1940sm3269357edi.29.2023.12.10.19.44.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 10 Dec 2023 19:44:20 -0800 (PST) Message-ID: <2cadfffa-00bf-4e6a-bfce-9cc654b042a1@linaro.org> Date: Mon, 11 Dec 2023 03:44:18 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories support in spi-nor Content-Language: en-US To: "Mahapatra, Amit Kumar" , "broonie@kernel.org" , "pratyush@kernel.org" , "miquel.raynal@bootlin.com" , "richard@nod.at" , "vigneshr@ti.com" , "sbinding@opensource.cirrus.com" , "lee@kernel.org" , "james.schulman@cirrus.com" , "david.rhodes@cirrus.com" , "rf@opensource.cirrus.com" , "perex@perex.cz" , "tiwai@suse.com" Cc: "linux-spi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "michael@walle.cc" , "linux-mtd@lists.infradead.org" , "nicolas.ferre@microchip.com" , "alexandre.belloni@bootlin.com" , "claudiu.beznea@tuxon.dev" , "Simek, Michal" , "linux-arm-kernel@lists.infradead.org" , "alsa-devel@alsa-project.org" , "patches@opensource.cirrus.com" , "linux-sound@vger.kernel.org" , "git (AMD-Xilinx)" , "amitrkcian2002@gmail.com" References: <20231125092137.2948-1-amit.kumar-mahapatra@amd.com> <20231125092137.2948-8-amit.kumar-mahapatra@amd.com> <9f577482-30d9-4e1d-9469-812d323b18c6@linaro.org> From: Tudor Ambarus In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Message-ID-Hash: YP2EMBXBO4GWLFJ5R2XCKGKMPB3UBA3K X-Message-ID-Hash: YP2EMBXBO4GWLFJ5R2XCKGKMPB3UBA3K X-MailFrom: tudor.ambarus@linaro.org X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.9 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: On 12/8/23 17:06, Mahapatra, Amit Kumar wrote: > Hello Tudor, Hi! > >> -----Original Message----- >> From: Tudor Ambarus >> Sent: Wednesday, December 6, 2023 8:14 PM >> To: Mahapatra, Amit Kumar ; >> broonie@kernel.org; pratyush@kernel.org; miquel.raynal@bootlin.com; >> richard@nod.at; vigneshr@ti.com; sbinding@opensource.cirrus.com; >> lee@kernel.org; james.schulman@cirrus.com; david.rhodes@cirrus.com; >> rf@opensource.cirrus.com; perex@perex.cz; tiwai@suse.com >> Cc: linux-spi@vger.kernel.org; linux-kernel@vger.kernel.org; >> michael@walle.cc; linux-mtd@lists.infradead.org; >> nicolas.ferre@microchip.com; alexandre.belloni@bootlin.com; >> claudiu.beznea@tuxon.dev; Simek, Michal ; linux- >> arm-kernel@lists.infradead.org; alsa-devel@alsa-project.org; >> patches@opensource.cirrus.com; linux-sound@vger.kernel.org; git (AMD- >> Xilinx) ; amitrkcian2002@gmail.com >> Subject: Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories support >> in spi-nor >> >> >> >> On 12/6/23 14:30, Tudor Ambarus wrote: >>> Hi, Amit, >>> >>> On 11/25/23 09:21, Amit Kumar Mahapatra wrote: >>>> Each flash that is connected in stacked mode should have a separate >>>> parameter structure. So, the flash parameter member(*params) of the >>>> spi_nor structure is changed to an array (*params[2]). The array is >>>> used to store the parameters of each flash connected in stacked >> configuration. >>>> >>>> The current implementation assumes that a maximum of two flashes are >>>> connected in stacked mode and both the flashes are of same make but >>>> can differ in sizes. So, except the sizes all other flash parameters >>>> of both the flashes are identical. >>> >>> Do you plan to add support for different flashes in stacked mode? If >>> not, wouldn't it be simpler to have just an array of flash sizes >>> instead of duplicating the entire params struct? >>> >>>> >>>> SPI-NOR is not aware of the chip_select values, for any incoming >>>> request SPI-NOR will decide the flash index with the help of >>>> individual flash size and the configuration type (single/stacked). >>>> SPI-NOR will pass on the flash index information to the SPI core & >>>> SPI driver by setting the appropriate bit in >>>> nor->spimem->spi->cs_index_mask. For example, if nth bit of >>>> nor->spimem->spi->cs_index_mask is set then the driver would >>>> assert/de-assert spi->chip_slect[n]. >>>> >>>> Signed-off-by: Amit Kumar Mahapatra > mahapatra@amd.com> >>>> --- >>>> drivers/mtd/spi-nor/core.c | 272 +++++++++++++++++++++++++++++------- >>>> drivers/mtd/spi-nor/core.h | 4 + >>>> include/linux/mtd/spi-nor.h | 15 +- >>>> 3 files changed, 240 insertions(+), 51 deletions(-) >>>> >>>> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c >>>> index 93ae69b7ff83..e990be7c7eb6 100644 >>>> --- a/drivers/mtd/spi-nor/core.c >>>> +++ b/drivers/mtd/spi-nor/core.c >>> >>> cut >>> >>>> @@ -2905,7 +3007,10 @@ static void spi_nor_init_fixup_flags(struct >>>> spi_nor *nor) static int spi_nor_late_init_params(struct spi_nor >>>> *nor) { >>>> struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, >> 0); >>>> - int ret; >>>> + struct device_node *np = spi_nor_get_flash_node(nor); >>>> + u64 flash_size[SNOR_FLASH_CNT_MAX]; >>>> + u32 idx = 0; >>>> + int rc, ret; >>>> >>>> if (nor->manufacturer && nor->manufacturer->fixups && >>>> nor->manufacturer->fixups->late_init) { @@ -2937,6 +3042,44 @@ >>>> static int spi_nor_late_init_params(struct spi_nor *nor) >>>> if (params->n_banks > 1) >>>> params->bank_size = div64_u64(params->size, params- >>> n_banks); >>>> >>>> + nor->num_flash = 0; >>>> + >>>> + /* >>>> + * The flashes that are connected in stacked mode should be of same >> make. >>>> + * Except the flash size all other properties are identical for all the >>>> + * flashes connected in stacked mode. >>>> + * The flashes that are connected in parallel mode should be identical. >>>> + */ >>>> + while (idx < SNOR_FLASH_CNT_MAX) { >>>> + rc = of_property_read_u64_index(np, "stacked-memories", >> idx, >>>> +&flash_size[idx]); >> >> also, it's not clear to me why you read this property multiple times. >> Have you sent a device tree patch somewhere? It will help me understand >> what you're trying to achieve. > > Miquel submitted the device tree patch; here is the series. > https://lore.kernel.org/all/20220126112608.955728-1-miquel.raynal@bootlin.com/ > oh, yes, I remember seeing this on the ml, but I couldn't allocate time to review it. Looking at: https://lore.kernel.org/all/20220126112608.955728-4-miquel.raynal@bootlin.com/ Flash size is not necessary for SPI NORs, as it can be discovered via SFDP. And spi-max-frequency should have been specified for all flashes, as I expect it can differ. At least so that the controller chooses the minimum frequency from all the max (if it can't operate the stacks at different frequencies). Cheers, ta