From: Brian Rhodes <bgr@acdstar.com>
To: Mark Brown <broonie@sirena.org.uk>
Cc: alsa-devel@alsa-project.org
Subject: Re: ASoC: pxa2xx-i2s
Date: Thu, 22 Jan 2009 11:03:42 -0600 [thread overview]
Message-ID: <4978A6EE.4090107@acdstar.com> (raw)
In-Reply-To: <20090121222718.GA23539@sirena.org.uk>
Mark Brown wrote:
> On Wed, Jan 21, 2009 at 02:13:12PM -0600, Brian Rhodes wrote:
>
>
>> No, the 270 is the clock master on the I2S bus. The codec is sourcing
>> the clock input using the PLL. I apologize for being unclear.
>>
>
> I think it's me that's not being clear, sorry - I'm trying to find out
> is if the LRCLK and BCLK signals on the I2S bus itself are being driven
> by the codec or by the I2S controller. If the codec driver is the clock
> master then your earlier speculation that your problems with the I2S
> controller may be due to some interaction with the codec driver are more
> likely to be true.
LCRK and BCLK are configured as inputs. The Codec is not the bus master.
next prev parent reply other threads:[~2009-01-22 17:03 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-01-20 14:31 ASoC: pxa2xx-i2s Brian Rhodes
2009-01-20 15:44 ` Karl Beldan
2009-01-20 17:04 ` Brian Rhodes
2009-01-20 22:24 ` Brian Rhodes
2009-01-21 13:23 ` Mark Brown
[not found] ` <49775159.7070708@linespeed.net>
2009-01-21 19:32 ` Mark Brown
2009-01-21 20:13 ` Brian Rhodes
2009-01-21 22:27 ` Mark Brown
2009-01-22 17:03 ` Brian Rhodes [this message]
2009-01-23 16:50 ` Brian Rhodes
2009-01-23 16:58 ` Mark Brown
2009-05-08 22:13 ` Karl Beldan
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