From mboxrd@z Thu Jan 1 00:00:00 1970 From: Liam Girdwood Subject: Re: [PATCH 1/2] ASoC: tlv320aic3x: Don't sync first two registers from register cache Date: Mon, 23 May 2011 10:39:31 +0100 Message-ID: <4DDA2B53.7020109@ti.com> References: <1305899558-21719-1-git-send-email-jhnikula@gmail.com> <4DD7DAAA.3070504@ti.com> <20110522102112.GA21476@opensource.wolfsonmicro.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by alsa0.perex.cz (Postfix) with ESMTP id E772C1037E3 for ; Mon, 23 May 2011 11:39:36 +0200 (CEST) In-Reply-To: <20110522102112.GA21476@opensource.wolfsonmicro.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: alsa-devel-bounces@alsa-project.org Errors-To: alsa-devel-bounces@alsa-project.org To: Mark Brown Cc: "alsa-devel@alsa-project.org" List-Id: alsa-devel@alsa-project.org On 22/05/11 11:21, Mark Brown wrote: > On Sat, May 21, 2011 at 04:30:50PM +0100, Liam Girdwood wrote: > >> Both > >> Acked-by: Liam Girdwood > > Acked-by: Mark Brown > > As they're TI devices I guess you'd want to apply them? Yep, both now applied. Thanks Liam