Re: snd soc spi read/write

Mark Brown
2011-08-05T05:42:12Z

On Fri, Aug 05, 2011 at 10:24:43AM +0800, Scott Jiang wrote:

> hw_write use 16bit reg, cache use 8bit reg, in former version
>
> data[0] = (reg >> 8) & 0xff;
> data[1] = reg & 0xff;
> data[2] = value;
>
> reg &= 0xff;
> if (reg < codec->reg_cache_size)
> cache[reg] = value;
>
> ret = codec->hw_write(codec->control_data, data, 3);

Which is just obviously insane and buggy as with that code the same
cache slot will be used for 256 different registers that differ only in
the upper byte.

> now in do_hw_write
> if (!snd_soc_codec_volatile_register(codec, reg) &&
> reg < codec->driver->reg_cache_size &&
> !codec->cache_bypass) {
> ret = snd_soc_cache_write(codec, reg, value);
> if (ret < 0)
> return -1;
> }
> reg > reg_cache_size, so will not write to cache

Which is exactly what we'd expect - we won't have allocated a cache
beyond register reg_cache_size and the driver is telling us not to cache
those registers.

> > Note that all this code will be replaced with regmap for 3.2.

> Do you mean I must update to 3.2 to solve this problem?

I don't see any problem here. What is the problem you're experiencing?