From: Lars-Peter Clausen <lars@metafoo.de>
To: "Andreas Irestål" <andreas.irestal@axis.com>
Cc: liam.r.girdwood@linux.intel.com,
"Andreas Irestål" <andire@axis.com>,
alsa-devel@alsa-project.org, broonie@kernel.org
Subject: Re: [PATCH] ASoC: adau17x1: Cache writes when core clock is disabled
Date: Thu, 4 Feb 2016 18:24:08 +0100 [thread overview]
Message-ID: <56B38938.40000@metafoo.de> (raw)
In-Reply-To: <56B388DC.40601@metafoo.de>
On 02/04/2016 06:22 PM, Lars-Peter Clausen wrote:
[...]
>> + /* Enable cache only mode as we could miss writes before bias level
>> + * reaches standby and the core clock is enabled */
>> + regcache_cache_only(regmap, true);
>> +
>
> There are a few register writes before this where the hardware configuration
> is setup. When I look at my test setup those writes seem to go through, even
> though they shouldn't according to what you say (and to what is written in
> the datasheet).
>
> On the other hand I've never seen the issue you are having either and I've
> tested both master and slave configuration of the device. Maybe something
> changed in the silicon in newer revisions of the device. Can you take a look
> whether the hardware configuration is correctly applied for you?
Ah, no, ignore that. Those writes happen later on.
next prev parent reply other threads:[~2016-02-04 17:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-04 14:05 [PATCH] ASoC: adau17x1: Cache writes when core clock is disabled Andreas Irestål
2016-02-04 17:22 ` Lars-Peter Clausen
2016-02-04 17:24 ` Lars-Peter Clausen [this message]
2016-02-04 19:01 ` Andreas Irestål
2016-02-04 19:34 ` Mark Brown
2016-02-05 13:35 ` Applied "ASoC: adau17x1: Cache writes when core clock is disabled" to the asoc tree Mark Brown
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