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d="scan'208";a="307147466" Received: from irsmsx605.ger.corp.intel.com ([163.33.146.138]) by orsmga006.jf.intel.com with ESMTP; 16 Sep 2020 11:30:29 -0700 Received: from irsmsx601.ger.corp.intel.com (163.33.146.7) by IRSMSX605.ger.corp.intel.com (163.33.146.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 16 Sep 2020 19:30:27 +0100 Received: from irsmsx601.ger.corp.intel.com ([163.33.146.7]) by irsmsx601.ger.corp.intel.com ([163.33.146.7]) with mapi id 15.01.1713.004; Wed, 16 Sep 2020 19:30:27 +0100 From: "Rojewski, Cezary" To: Andy Shevchenko Subject: RE: [PATCH v5 01/13] ASoC: Intel: Add catpt device Thread-Topic: [PATCH v5 01/13] ASoC: Intel: Add catpt device Thread-Index: AQHWi32GW37jr4EJj0CkLtYrpbvLFKlrU1CAgAAZhACAACqUUA== Date: Wed, 16 Sep 2020 18:30:27 +0000 Message-ID: <9050ad4f60764a55a98579e494bd53f0@intel.com> References: <20200915162944.16241-1-cezary.rojewski@intel.com> <20200915162944.16241-2-cezary.rojewski@intel.com> <20200916152455.GP3956970@smile.fi.intel.com> <20200916165614.GC3956970@smile.fi.intel.com> In-Reply-To: <20200916165614.GC3956970@smile.fi.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 x-originating-ip: [163.33.253.164] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "pierre-louis.bossart@linux.intel.com" , "alsa-devel@alsa-project.org" , "Kaczmarski, Filip" , "N, Harshapriya" , "Barlik, Marcin" , "zwisler@google.com" , "lgirdwood@gmail.com" , "tiwai@suse.com" , "Proborszcz, Filip" , "broonie@kernel.org" , "amadeuszx.slawinski@linux.intel.com" , "Wasko, Michal" , "cujomalainey@chromium.org" , "Hejmowski, Krzysztof" , "Papierkowski, Piotr \(Habana\)" , "Gopal, Vamshi Krishna" X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" > On Wed, Sep 16, 2020 at 06:24:56PM +0300, Andy Shevchenko wrote: > > On Tue, Sep 15, 2020 at 06:29:32PM +0200, Cezary Rojewski wrote: > > > Declare base structures, registers and device routines for the catpt > > > solution. Catpt deprecates and is a direct replacement for > > > sound/soc/intel/haswell. Supports Lynxpoint and Wildcat Point both. > > > > Few nit-picks below. Overall looks good, FWIW, > > Reviewed-by: Andy Shevchenko >=20 > Actually hold on. See below. >=20 > > > +void catpt_sram_init(struct resource *sram, u32 start, u32 size); > > > +void catpt_sram_free(struct resource *sram); > > > +struct resource * > > > +catpt_request_region(struct resource *root, resource_size_t size); >=20 > These seems dangling declarations that has to be moved to the > corresponding > patch. Please, revisit entire series to be sure that: >=20 > - each patch doesn't add any warnings on W=3D1 > - each patch doesn't have dangling stuff > - each patch is bisectable for compilation and run-time >=20 TLDR: you want patches: 6/13 ASoC: Intel: catpt: PCM operations 5/13 ASoC: Intel: catpt: Add IPC messages 4/13 ASoC: Intel: catpt: Implement IPC protocol 3/13 ASoC: Intel: catpt: Firmware loading and context restore 2/13 ASoC: Intel: catpt: Define DSP operations 1/13 ASoC: Intel: Add catpt device squashed. There is no other way to achieve that without combining all the core-code together. fs and traces can be provided separately, but not the first 6. Czarek