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[86.26.103.58]) by smtp.googlemail.com with ESMTPSA id z14sm2337734wrp.70.2021.12.02.03.22.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Dec 2021 03:22:14 -0800 (PST) Subject: Re: [PATCH v6 03/10] ASoC: qcom: Add register definition for codec rddma and wrdma To: Srinivasa Rao Mandadapu , agross@kernel.org, bjorn.andersson@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, plai@codeaurora.org, bgoswami@codeaurora.org, perex@perex.cz, tiwai@suse.com, rohitkr@codeaurora.org, linux-arm-msm@vger.kernel.org, alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, swboyd@chromium.org, judyhsiao@chromium.org References: <1637928282-2819-1-git-send-email-srivasam@codeaurora.org> <1637928282-2819-4-git-send-email-srivasam@codeaurora.org> <3bb4aea6-2f47-8b6b-e7a9-1518d478e32d@linaro.org> From: Srinivas Kandagatla Message-ID: <928c419e-ae92-38bd-3974-e81efbe301ff@linaro.org> Date: Thu, 2 Dec 2021 11:22:13 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Cc: Venkata Prasad Potturu X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On 02/12/2021 10:55, Srinivasa Rao Mandadapu wrote: >>>   +/* LPAIF RXTX IRQ */ >>> +#define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port, dai_id) \ >>> +        ((dai_id == LPASS_CDC_DMA_RX0 || dai_id == >>> LPASS_CDC_DMA_TX3) ? \ >>> +        (v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * >>> (port)) : \ >>> +        (v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port))) >>> + >>> +#define LPAIF_RXTX_IRQEN_REG(v, port, dai_id) >>> LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port, dai_id) >>> +#define LPAIF_RXTX_IRQSTAT_REG(v, port, dai_id) >>> LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port, dai_id) >>> +#define LPAIF_RXTX_IRQCLEAR_REG(v, port, dai_id) >>> LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port, dai_id) >>> + >> >> How about doing like this: >> >> >> /* LPAIF RXTX IRQ */ >> #define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \ >>         (v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * (port)) >> >> #define LPAIF_RXTX_IRQEN_REG(v, port, dai_id) >> LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port) >> #define LPAIF_RXTX_IRQSTAT_REG(v, port, dai_id) >> LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port) >> #define LPAIF_RXTX_IRQCLEAR_REG(v, port, dai_id) >> LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port) >> >> /* LPAIF VA IRQ */ >> #define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \ >>         (v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port)) >> >> #define LPAIF_VA_IRQEN_REG(v, port, dai_id) LPAIF_VA_IRQ_REG_ADDR(v, >> 0x0, port) >> #define LPAIF_VA_IRQSTAT_REG(v, port, dai_id) LPAIF_VA_IRQ_REG_ADDR(v, >> 0x4, port) >> #define LPAIF_VA_IRQCLEAR_REG(v, port, dai_id) >> LPAIF_VA_IRQ_REG_ADDR(v, 0xC, port) >> > With this we are seeing number macros increasing. How about handling Its okay to add new macros, this makes them much clear to the reader and inline with rest of the macros in the file. --srini > like below. >> lpass.h: > > static inline bool is_rxtx_cdc_dma_port(int dai_id) > { > >     switch (dai_id) { >         case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: >         case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: >             return true; >         default: >             return false; >       } > } > > > Usage: > > #define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port, dai_id) \ > is_rxtx_cdc_dma_port(dai_id) ? \ > (v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * (port)) : \ > (v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port)) > >