[PATCH 0/5] ASoC: Fix smdk64xx-wm8580 problems

[PATCH 0/5] ASoC: Fix smdk64xx-wm8580 problems

[Seungwhan Youn]

Hi,

This patch serise fix some problems in smdk64xx board when it use
I2S with wm8580.

 o ADC source clock setting is set to use MCLK, It makes that
   wm8580 cannot make BCLK and LRCLK for playback and capture.
 o When application set some sampling freq. - 8kHz, 11.025kHz,
   audio doesn't work correctly with broken sound. Because
   wm8580 always set BCLK_RATE and LRCLK_RATE as a default value
   , BCLK_RATE - 256fs and LRCLK_RATE - 64 BCLKs per LRCLK. So,
   BCLK_RATE and LRCLK_RATE setting on wm8580 is not match to
   make these sampling freq. on wm8580 master mode.

So, to solve these problems, this patch apply followings:

 o Support ADC source clock setting on wm8580.
 o Enable to select BCLK_RATE and LRCLK_RATE value on wm8580.
 o Fix smdk-wm8580 machine code to support new features of wm8580.


The following patch series contains:

[PATCH 1/5] ASoC: wm8580: Add to support ADC clock source setting
[PATCH 2/5] ASoC: S3C64XX: Add ADC source clock setting
[PATCH 3/5] ASoC: wm8580: Fix Master Mode BCLK rates names
[PATCH 4/5] ASoC: wm8580: Add to support Master Mode Rates
[PATCH 5/5] ASoC: S3C64XX: Fix to support BCLK, LRCLK rates setting

Thanks,

Claude

[PATCH 1/5] ASoC: wm8580: Add to support ADC clock source setting

[Seungwhan Youn]

This patch adds to support additional ADC clock source setting
with R8 register for CLKSRC on wm8580.

Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
---
 sound/soc/codecs/wm8580.c |   33 +++++++++++++++++++++++++++++++++
 sound/soc/codecs/wm8580.h |   16 +++++++++-------
 2 files changed, 42 insertions(+), 7 deletions(-)

diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
index c3571ee..e342da5 100644
--- a/sound/soc/codecs/wm8580.c
+++ b/sound/soc/codecs/wm8580.c
@@ -110,6 +110,12 @@
 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
 
+#define WM8580_CLKSEL_ADC_CLKSEL_MASK     0x0c
+#define WM8580_CLKSEL_ADC_CLKSEL_ADCMCLK  0x00
+#define WM8580_CLKSEL_ADC_CLKSEL_PLLA     0x04
+#define WM8580_CLKSEL_ADC_CLKSEL_PLLB     0x08
+#define WM8580_CLKSEL_ADC_CLKSEL_MCLK     0x0c
+
 /* AIF control 1 (registers 9h-bh) */
 #define WM8580_AIF_RATE_MASK       0x7
 #define WM8580_AIF_RATE_128        0x0
@@ -672,6 +678,33 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 		snd_soc_write(codec, WM8580_PLLB4, reg);
 		break;
 
+	case WM8580_ADC_CLKSEL:
+		reg = snd_soc_read(codec, WM8580_CLKSEL);
+		reg &= ~WM8580_CLKSEL_ADC_CLKSEL_MASK;
+
+		switch (div) {
+		case WM8580_CLKSRC_ADCMCLK:
+			reg |= WM8580_CLKSEL_ADC_CLKSEL_ADCMCLK;
+			break;
+
+		case WM8580_CLKSRC_MCLK:
+			reg |= WM8580_CLKSEL_ADC_CLKSEL_MCLK;
+			break;
+
+		case WM8580_CLKSRC_PLLA:
+			reg |= WM8580_CLKSEL_ADC_CLKSEL_PLLA;
+			break;
+
+		case WM8580_CLKSRC_PLLB:
+			reg |= WM8580_CLKSEL_ADC_CLKSEL_PLLB;
+			break;
+
+		default:
+			return -EINVAL;
+		}
+		snd_soc_write(codec, WM8580_CLKSEL, reg);
+		break;
+
 	default:
 		return -EINVAL;
 	}
diff --git a/sound/soc/codecs/wm8580.h b/sound/soc/codecs/wm8580.h
index 0dfb5dd..aeb65ef 100644
--- a/sound/soc/codecs/wm8580.h
+++ b/sound/soc/codecs/wm8580.h
@@ -20,13 +20,15 @@
 
 #define WM8580_MCLK       1
 #define WM8580_DAC_CLKSEL 2
-#define WM8580_CLKOUTSRC  3
-
-#define WM8580_CLKSRC_MCLK 1
-#define WM8580_CLKSRC_PLLA 2
-#define WM8580_CLKSRC_PLLB 3
-#define WM8580_CLKSRC_OSC  4
-#define WM8580_CLKSRC_NONE 5
+#define WM8580_ADC_CLKSEL 3
+#define WM8580_CLKOUTSRC  4
+
+#define WM8580_CLKSRC_MCLK    1
+#define WM8580_CLKSRC_ADCMCLK 2
+#define WM8580_CLKSRC_PLLA    3
+#define WM8580_CLKSRC_PLLB    4
+#define WM8580_CLKSRC_OSC     5
+#define WM8580_CLKSRC_NONE    6
 
 #define WM8580_DAI_PAIFRX 0
 #define WM8580_DAI_PAIFTX 1
-- 
1.6.2.5

[PATCH 2/5] ASoC: S3C64XX: Add ADC source clock setting

[Seungwhan Youn]

This patch adds ADC source clock setting to set wm8580 use ADC
source clock to ADC_MCLK.

Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
---
 sound/soc/s3c24xx/smdk64xx_wm8580.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/sound/soc/s3c24xx/smdk64xx_wm8580.c b/sound/soc/s3c24xx/smdk64xx_wm8580.c
index 07e8e51..39bb701 100644
--- a/sound/soc/s3c24xx/smdk64xx_wm8580.c
+++ b/sound/soc/s3c24xx/smdk64xx_wm8580.c
@@ -113,6 +113,12 @@ static int smdk64xx_hw_params(struct snd_pcm_substream *substream,
 	if (ret < 0)
 		return ret;
 
+	/* Explicitly set WM8580-ADC to source from ADCMCLK */
+	ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_ADC_CLKSEL,
+					WM8580_CLKSRC_ADCMCLK);
+	if (ret < 0)
+		return ret;
+
 	ret = snd_soc_dai_set_pll(codec_dai, WM8580_PLLA, 0,
 					SMDK64XX_WM8580_FREQ, pll_out);
 	if (ret < 0)
-- 
1.6.2.5

[PATCH 3/5] ASoC: wm8580: Fix Master Mode BCLK rates names

[Seungwhan Youn]

This patch fix BCLK rates name from old manual. As a recently
wm8580 manual (Rel. March 2009, Rev 4.7), wm8580 supports 4
BCLK rates, 64, 32, 16 and System Clock per LRCLK. So, this
patch apply to match BCLK rates with manual.

Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
---
 sound/soc/codecs/wm8580.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
index e342da5..d282eb3 100644
--- a/sound/soc/codecs/wm8580.c
+++ b/sound/soc/codecs/wm8580.c
@@ -128,8 +128,8 @@
 
 #define WM8580_AIF_BCLKSEL_MASK   0x18
 #define WM8580_AIF_BCLKSEL_64     0x00
-#define WM8580_AIF_BCLKSEL_128    0x08
-#define WM8580_AIF_BCLKSEL_256    0x10
+#define WM8580_AIF_BCLKSEL_32     0x08
+#define WM8580_AIF_BCLKSEL_16     0x10
 #define WM8580_AIF_BCLKSEL_SYSCLK 0x18
 
 #define WM8580_AIF_MS             0x20
-- 
1.6.2.5

[PATCH 4/5] ASoC: wm8580: Add to support Master Mode Rates

[Seungwhan Youn]

This patch adds to support Master Mode LRCLK, BCLK rates
setting for wm8580.

Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
---
 sound/soc/codecs/wm8580.c |   51 +++++++++++++++++++++++++++++++++++++++++++++
 sound/soc/codecs/wm8580.h |    2 +
 2 files changed, 53 insertions(+), 0 deletions(-)

diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
index d282eb3..a2bb2a4 100644
--- a/sound/soc/codecs/wm8580.c
+++ b/sound/soc/codecs/wm8580.c
@@ -705,6 +705,57 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 		snd_soc_write(codec, WM8580_CLKSEL, reg);
 		break;
 
+	case WM8580_LRCLK_RATE:
+		reg = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->id);
+		reg &= ~WM8580_AIF_RATE_MASK;
+		switch (div) {
+		case 128:
+			reg |= WM8580_AIF_RATE_128;
+			break;
+		case 192:
+			reg |= WM8580_AIF_RATE_192;
+			break;
+		case 256:
+			reg |= WM8580_AIF_RATE_256;
+			break;
+		case 384:
+			reg |= WM8580_AIF_RATE_384;
+			break;
+		case 512:
+			reg |= WM8580_AIF_RATE_512;
+			break;
+		case 768:
+			reg |= WM8580_AIF_RATE_768;
+			break;
+		case 1152:
+			reg |= WM8580_AIF_RATE_1152;
+			break;
+		default:
+			return -EINVAL;
+		}
+		snd_soc_write(codec, WM8580_PAIF1 + codec_dai->id, reg);
+		break;
+
+	case WM8580_BCLK_RATE:
+		reg = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->id);
+		reg &= ~WM8580_AIF_BCLKSEL_MASK;
+		switch (div) {
+		case 64:
+			reg |= WM8580_AIF_BCLKSEL_64;
+			break;
+		case 32:
+			reg |= WM8580_AIF_BCLKSEL_32;
+			break;
+		case 16:
+			reg |= WM8580_AIF_BCLKSEL_16;
+			break;
+		default:
+			reg |= WM8580_AIF_BCLKSEL_SYSCLK;
+			break;
+		}
+		snd_soc_write(codec, WM8580_PAIF1 + codec_dai->id, reg);
+		break;
+
 	default:
 		return -EINVAL;
 	}
diff --git a/sound/soc/codecs/wm8580.h b/sound/soc/codecs/wm8580.h
index aeb65ef..2272e36 100644
--- a/sound/soc/codecs/wm8580.h
+++ b/sound/soc/codecs/wm8580.h
@@ -22,6 +22,8 @@
 #define WM8580_DAC_CLKSEL 2
 #define WM8580_ADC_CLKSEL 3
 #define WM8580_CLKOUTSRC  4
+#define WM8580_LRCLK_RATE 5
+#define WM8580_BCLK_RATE  6
 
 #define WM8580_CLKSRC_MCLK    1
 #define WM8580_CLKSRC_ADCMCLK 2
-- 
1.6.2.5

[PATCH 5/5] ASoC: S3C64XX: Fix to support BCLK, LRCLK rates setting

[Seungwhan Youn]

This patch fix to support BCLK and LRCLK rates setting as
wm8580 Master mode. After apply this patch, LRCLK and BCLK
signal appears correctly from wm8580 in some freq., 8kHz
and 11.025kHz, on SMDK board.

Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
---
 sound/soc/s3c24xx/smdk64xx_wm8580.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/s3c24xx/smdk64xx_wm8580.c b/sound/soc/s3c24xx/smdk64xx_wm8580.c
index 39bb701..f3dbdfb 100644
--- a/sound/soc/s3c24xx/smdk64xx_wm8580.c
+++ b/sound/soc/s3c24xx/smdk64xx_wm8580.c
@@ -124,11 +124,11 @@ static int smdk64xx_hw_params(struct snd_pcm_substream *substream,
 	if (ret < 0)
 		return ret;
 
-	ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_I2SV2_DIV_BCLK, bfs);
+	ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_BCLK_RATE, bfs);
 	if (ret < 0)
 		return ret;
 
-	ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_I2SV2_DIV_RCLK, rfs);
+	ret = snd_soc_dai_set_clkdiv(codec_dai,	WM8580_LRCLK_RATE, rfs);
 	if (ret < 0)
 		return ret;
 
-- 
1.6.2.5

Re: [PATCH 5/5] ASoC: S3C64XX: Fix to support BCLK, LRCLK rates setting

[Jassi Brar]

On Fri, Aug 6, 2010 at 9:36 AM, Seungwhan Youn <sw.youn@samsung.com> wrote:
> This patch fix to support BCLK and LRCLK rates setting as
> wm8580 Master mode. After apply this patch, LRCLK and BCLK
> signal appears correctly from wm8580 in some freq., 8kHz
> and 11.025kHz, on SMDK board.
>
> Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
> ---
>  sound/soc/s3c24xx/smdk64xx_wm8580.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/sound/soc/s3c24xx/smdk64xx_wm8580.c b/sound/soc/s3c24xx/smdk64xx_wm8580.c
> index 39bb701..f3dbdfb 100644
> --- a/sound/soc/s3c24xx/smdk64xx_wm8580.c
> +++ b/sound/soc/s3c24xx/smdk64xx_wm8580.c
> @@ -124,11 +124,11 @@ static int smdk64xx_hw_params(struct snd_pcm_substream *substream,
>        if (ret < 0)
>                return ret;
>
> -       ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_I2SV2_DIV_BCLK, bfs);
> +       ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_BCLK_RATE, bfs);
>        if (ret < 0)
>                return ret;
>
> -       ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_I2SV2_DIV_RCLK, rfs);
> +       ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_LRCLK_RATE, rfs);
>        if (ret < 0)
>                return ret;

http://mailman.alsa-project.org/pipermail/alsa-devel/2009-September/021005.html
is what I meant a few days ago when I said it should be done properly.

Also, I am not sure if we can do without setting RFS,BFS on CPU side
even in slave mode. We need to confirm.
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Re: [PATCH 1/5] ASoC: wm8580: Add to support ADC clock source setting

[Jassi Brar]

On Fri, Aug 6, 2010 at 9:18 AM, Seungwhan Youn <sw.youn@samsung.com> wrote:
> This patch adds to support additional ADC clock source setting
> with R8 register for CLKSRC on wm8580.
>
> Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
> ---
>  sound/soc/codecs/wm8580.c |   33 +++++++++++++++++++++++++++++++++
>  sound/soc/codecs/wm8580.h |   16 +++++++++-------
>  2 files changed, 42 insertions(+), 7 deletions(-)
>
> diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
> index c3571ee..e342da5 100644
> --- a/sound/soc/codecs/wm8580.c
> +++ b/sound/soc/codecs/wm8580.c
> @@ -110,6 +110,12 @@
>  #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
>  #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
>
> +#define WM8580_CLKSEL_ADC_CLKSEL_MASK     0x0c
> +#define WM8580_CLKSEL_ADC_CLKSEL_ADCMCLK  0x00
> +#define WM8580_CLKSEL_ADC_CLKSEL_PLLA     0x04
> +#define WM8580_CLKSEL_ADC_CLKSEL_PLLB     0x08
> +#define WM8580_CLKSEL_ADC_CLKSEL_MCLK     0x0c
> +
>  /* AIF control 1 (registers 9h-bh) */
>  #define WM8580_AIF_RATE_MASK       0x7
>  #define WM8580_AIF_RATE_128        0x0
> @@ -672,6 +678,33 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
>                snd_soc_write(codec, WM8580_PLLB4, reg);
>                break;
>
> +       case WM8580_ADC_CLKSEL:
> +               reg = snd_soc_read(codec, WM8580_CLKSEL);
> +               reg &= ~WM8580_CLKSEL_ADC_CLKSEL_MASK;
> +
> +               switch (div) {
> +               case WM8580_CLKSRC_ADCMCLK:
> +                       reg |= WM8580_CLKSEL_ADC_CLKSEL_ADCMCLK;
> +                       break;
> +
> +               case WM8580_CLKSRC_MCLK:
> +                       reg |= WM8580_CLKSEL_ADC_CLKSEL_MCLK;
> +                       break;
> +
> +               case WM8580_CLKSRC_PLLA:
> +                       reg |= WM8580_CLKSEL_ADC_CLKSEL_PLLA;
> +                       break;
> +
> +               case WM8580_CLKSRC_PLLB:
> +                       reg |= WM8580_CLKSEL_ADC_CLKSEL_PLLB;
> +                       break;
> +
> +               default:
> +                       return -EINVAL;
> +               }
> +               snd_soc_write(codec, WM8580_CLKSEL, reg);
> +               break;
> +
>        default:
>                return -EINVAL;
>        }
> diff --git a/sound/soc/codecs/wm8580.h b/sound/soc/codecs/wm8580.h
> index 0dfb5dd..aeb65ef 100644
> --- a/sound/soc/codecs/wm8580.h
> +++ b/sound/soc/codecs/wm8580.h
> @@ -20,13 +20,15 @@
>
>  #define WM8580_MCLK       1
>  #define WM8580_DAC_CLKSEL 2
> -#define WM8580_CLKOUTSRC  3
> -
> -#define WM8580_CLKSRC_MCLK 1
> -#define WM8580_CLKSRC_PLLA 2
> -#define WM8580_CLKSRC_PLLB 3
> -#define WM8580_CLKSRC_OSC  4
> -#define WM8580_CLKSRC_NONE 5
> +#define WM8580_ADC_CLKSEL 3
> +#define WM8580_CLKOUTSRC  4
> +
> +#define WM8580_CLKSRC_MCLK    1
> +#define WM8580_CLKSRC_ADCMCLK 2
> +#define WM8580_CLKSRC_PLLA    3
> +#define WM8580_CLKSRC_PLLB    4
> +#define WM8580_CLKSRC_OSC     5
> +#define WM8580_CLKSRC_NONE    6
>
>  #define WM8580_DAI_PAIFRX 0
>  #define WM8580_DAI_PAIFTX 1

This is OK. Though I don't remember why it wasn't accepted when
I submitted a few months ago.
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Re: [PATCH 4/5] ASoC: wm8580: Add to support Master Mode Rates

[Jassi Brar]

On Fri, Aug 6, 2010 at 9:32 AM, Seungwhan Youn <sw.youn@samsung.com> wrote:
> This patch adds to support Master Mode LRCLK, BCLK rates
> setting for wm8580.
>
> Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
> ---
>  sound/soc/codecs/wm8580.c |   51 +++++++++++++++++++++++++++++++++++++++++++++
>  sound/soc/codecs/wm8580.h |    2 +
>  2 files changed, 53 insertions(+), 0 deletions(-)
>
> diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
> index d282eb3..a2bb2a4 100644
> --- a/sound/soc/codecs/wm8580.c
> +++ b/sound/soc/codecs/wm8580.c
> @@ -705,6 +705,57 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
>                snd_soc_write(codec, WM8580_CLKSEL, reg);
>                break;
>
> +       case WM8580_LRCLK_RATE:
> +               reg = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->id);
> +               reg &= ~WM8580_AIF_RATE_MASK;
> +               switch (div) {
> +               case 128:
> +                       reg |= WM8580_AIF_RATE_128;
> +                       break;
> +               case 192:
> +                       reg |= WM8580_AIF_RATE_192;
> +                       break;
> +               case 256:
> +                       reg |= WM8580_AIF_RATE_256;
> +                       break;
> +               case 384:
> +                       reg |= WM8580_AIF_RATE_384;
> +                       break;
> +               case 512:
> +                       reg |= WM8580_AIF_RATE_512;
> +                       break;
> +               case 768:
> +                       reg |= WM8580_AIF_RATE_768;
> +                       break;
> +               case 1152:
> +                       reg |= WM8580_AIF_RATE_1152;
> +                       break;
> +               default:
> +                       return -EINVAL;
> +               }
> +               snd_soc_write(codec, WM8580_PAIF1 + codec_dai->id, reg);
> +               break;
> +
> +       case WM8580_BCLK_RATE:
> +               reg = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->id);
> +               reg &= ~WM8580_AIF_BCLKSEL_MASK;
> +               switch (div) {
> +               case 64:
> +                       reg |= WM8580_AIF_BCLKSEL_64;
> +                       break;
> +               case 32:
> +                       reg |= WM8580_AIF_BCLKSEL_32;
> +                       break;
> +               case 16:
> +                       reg |= WM8580_AIF_BCLKSEL_16;
> +                       break;
> +               default:
> +                       reg |= WM8580_AIF_BCLKSEL_SYSCLK;
> +                       break;
> +               }
> +               snd_soc_write(codec, WM8580_PAIF1 + codec_dai->id, reg);
> +               break;
> +
>        default:
>                return -EINVAL;
>        }
> diff --git a/sound/soc/codecs/wm8580.h b/sound/soc/codecs/wm8580.h
> index aeb65ef..2272e36 100644
> --- a/sound/soc/codecs/wm8580.h
> +++ b/sound/soc/codecs/wm8580.h
> @@ -22,6 +22,8 @@
>  #define WM8580_DAC_CLKSEL 2
>  #define WM8580_ADC_CLKSEL 3
>  #define WM8580_CLKOUTSRC  4
> +#define WM8580_LRCLK_RATE 5
> +#define WM8580_BCLK_RATE  6
>
>  #define WM8580_CLKSRC_MCLK    1
>  #define WM8580_CLKSRC_ADCMCLK 2

Again.... http://mailman.alsa-project.org/pipermail/alsa-devel/2009-September/021005.html

Also IMO, WM8580_MCLKRATIO and  WM8580_BCLKRATIO sound better
than WM8580_LRCLK_RATE and WM8580_BCLK_RATE resp. That is if they
are to be accepted.
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Re: [PATCH 4/5] ASoC: wm8580: Add to support Master Mode Rates

[Seungwhan Youn]

On Fri, Aug 6, 2010 at 1:32 PM, Jassi Brar <jassisinghbrar@gmail.com> wrote:
> On Fri, Aug 6, 2010 at 9:32 AM, Seungwhan Youn <sw.youn@samsung.com> wrote:
>> This patch adds to support Master Mode LRCLK, BCLK rates
>> setting for wm8580.
>>
>> Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
>> ---
>>  sound/soc/codecs/wm8580.c |   51 +++++++++++++++++++++++++++++++++++++++++++++
>>  sound/soc/codecs/wm8580.h |    2 +
>>  2 files changed, 53 insertions(+), 0 deletions(-)
>>
>> diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
>> index d282eb3..a2bb2a4 100644
>> --- a/sound/soc/codecs/wm8580.c
>> +++ b/sound/soc/codecs/wm8580.c
>> @@ -705,6 +705,57 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
>>                snd_soc_write(codec, WM8580_CLKSEL, reg);
>>                break;
>>
>> +       case WM8580_LRCLK_RATE:
>> +               reg = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->id);
>> +               reg &= ~WM8580_AIF_RATE_MASK;
>> +               switch (div) {
>> +               case 128:
>> +                       reg |= WM8580_AIF_RATE_128;
>> +                       break;
>> +               case 192:
>> +                       reg |= WM8580_AIF_RATE_192;
>> +                       break;
>> +               case 256:
>> +                       reg |= WM8580_AIF_RATE_256;
>> +                       break;
>> +               case 384:
>> +                       reg |= WM8580_AIF_RATE_384;
>> +                       break;
>> +               case 512:
>> +                       reg |= WM8580_AIF_RATE_512;
>> +                       break;
>> +               case 768:
>> +                       reg |= WM8580_AIF_RATE_768;
>> +                       break;
>> +               case 1152:
>> +                       reg |= WM8580_AIF_RATE_1152;
>> +                       break;
>> +               default:
>> +                       return -EINVAL;
>> +               }
>> +               snd_soc_write(codec, WM8580_PAIF1 + codec_dai->id, reg);
>> +               break;
>> +
>> +       case WM8580_BCLK_RATE:
>> +               reg = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->id);
>> +               reg &= ~WM8580_AIF_BCLKSEL_MASK;
>> +               switch (div) {
>> +               case 64:
>> +                       reg |= WM8580_AIF_BCLKSEL_64;
>> +                       break;
>> +               case 32:
>> +                       reg |= WM8580_AIF_BCLKSEL_32;
>> +                       break;
>> +               case 16:
>> +                       reg |= WM8580_AIF_BCLKSEL_16;
>> +                       break;
>> +               default:
>> +                       reg |= WM8580_AIF_BCLKSEL_SYSCLK;
>> +                       break;
>> +               }
>> +               snd_soc_write(codec, WM8580_PAIF1 + codec_dai->id, reg);
>> +               break;
>> +
>>        default:
>>                return -EINVAL;
>>        }
>> diff --git a/sound/soc/codecs/wm8580.h b/sound/soc/codecs/wm8580.h
>> index aeb65ef..2272e36 100644
>> --- a/sound/soc/codecs/wm8580.h
>> +++ b/sound/soc/codecs/wm8580.h
>> @@ -22,6 +22,8 @@
>>  #define WM8580_DAC_CLKSEL 2
>>  #define WM8580_ADC_CLKSEL 3
>>  #define WM8580_CLKOUTSRC  4
>> +#define WM8580_LRCLK_RATE 5
>> +#define WM8580_BCLK_RATE  6
>>
>>  #define WM8580_CLKSRC_MCLK    1
>>  #define WM8580_CLKSRC_ADCMCLK 2
>
> Again.... http://mailman.alsa-project.org/pipermail/alsa-devel/2009-September/021005.html
>
> Also IMO, WM8580_MCLKRATIO and  WM8580_BCLKRATIO sound better
> than WM8580_LRCLK_RATE and WM8580_BCLK_RATE resp. That is if they
> are to be accepted.
>

When I write this code, I also think that name 'WM8580_MCLKRATIO' and
'WM8580_BCLKTRATIO'. But I think that 'WM8580_LRCLK_RATE' and
'WM8580_BCLK_RATE' is better because of these are named after wm8580
user manual, to avoid to be confused another guy who see this code
with wm8580 manual. If other guys think same as you, I'm ready to
modify this. :)


Thanks for your opinion. :)

Claude
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Re: [PATCH 5/5] ASoC: S3C64XX: Fix to support BCLK, LRCLK rates setting

[Seungwhan Youn]

On Fri, Aug 6, 2010 at 1:25 PM, Jassi Brar <jassisinghbrar@gmail.com> wrote:
> On Fri, Aug 6, 2010 at 9:36 AM, Seungwhan Youn <sw.youn@samsung.com> wrote:
>> This patch fix to support BCLK and LRCLK rates setting as
>> wm8580 Master mode. After apply this patch, LRCLK and BCLK
>> signal appears correctly from wm8580 in some freq., 8kHz
>> and 11.025kHz, on SMDK board.
>>
>> Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
>> ---
>>  sound/soc/s3c24xx/smdk64xx_wm8580.c |    4 ++--
>>  1 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/sound/soc/s3c24xx/smdk64xx_wm8580.c b/sound/soc/s3c24xx/smdk64xx_wm8580.c
>> index 39bb701..f3dbdfb 100644
>> --- a/sound/soc/s3c24xx/smdk64xx_wm8580.c
>> +++ b/sound/soc/s3c24xx/smdk64xx_wm8580.c
>> @@ -124,11 +124,11 @@ static int smdk64xx_hw_params(struct snd_pcm_substream *substream,
>>        if (ret < 0)
>>                return ret;
>>
>> -       ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_I2SV2_DIV_BCLK, bfs);
>> +       ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_BCLK_RATE, bfs);
>>        if (ret < 0)
>>                return ret;
>>
>> -       ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_I2SV2_DIV_RCLK, rfs);
>> +       ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_LRCLK_RATE, rfs);
>>        if (ret < 0)
>>                return ret;
>
> http://mailman.alsa-project.org/pipermail/alsa-devel/2009-September/021005.html
> is what I meant a few days ago when I said it should be done properly.

I see, if Mark's opinion is same as before, I think I can try to make
another patch for it. :)

>
> Also, I am not sure if we can do without setting RFS,BFS on CPU side
> even in slave mode. We need to confirm.
>

Okay, I agree to confirm this at the H/W design point of view.

Thanks,

Claude
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Re: [PATCH 1/5] ASoC: wm8580: Add to support ADC clock source setting

[Mark Brown]

On Fri, Aug 06, 2010 at 01:27:48PM +0900, Jassi Brar wrote:

> This is OK. Though I don't remember why it wasn't accepted when
> I submitted a few months ago.

IIRC it was part of a larger patch or patch series which had other
issues.

Re: [PATCH 2/5] ASoC: S3C64XX: Add ADC source clock setting

[Mark Brown]

On Fri, Aug 06, 2010 at 09:21:04AM +0900, Seungwhan Youn wrote:
> This patch adds ADC source clock setting to set wm8580 use ADC
> source clock to ADC_MCLK.
> 
> Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
> ---
>  sound/soc/s3c24xx/smdk64xx_wm8580.c |    6 ++++++

This isn't a patch for S3C64xx, this is a patch for the SMDK boards.

Re: [PATCH 5/5] ASoC: S3C64XX: Fix to support BCLK, LRCLK rates setting

[Mark Brown]

On Fri, Aug 06, 2010 at 03:02:49PM +0900, Seungwhan Youn wrote:

> I see, if Mark's opinion is same as before, I think I can try to make
> another patch for it. :)

I will look at this myself, the major blocker on doing so had been that
for many kernel releases it was not possible to use the IISv4 interface
since the support for the IISv4 main clock didn't get merged so every
time I spent any time on this it was all consumed implementing that and
resubmitting changes for that.  That appears to be sorted in at least
2.6.34 so I can now run tests much more easily.

Re: [PATCH 5/5] ASoC: S3C64XX: Fix to support BCLK, LRCLK rates setting

[Seungwhan Youn]

On Fri, Aug 6, 2010 at 8:17 PM, Mark Brown
<broonie@opensource.wolfsonmicro.com> wrote:
> On Fri, Aug 06, 2010 at 03:02:49PM +0900, Seungwhan Youn wrote:
>
>> I see, if Mark's opinion is same as before, I think I can try to make
>> another patch for it. :)
>
> I will look at this myself, the major blocker on doing so had been that
> for many kernel releases it was not possible to use the IISv4 interface
> since the support for the IISv4 main clock didn't get merged so every
> time I spent any time on this it was all consumed implementing that and
> resubmitting changes for that.  That appears to be sorted in at least
> 2.6.34 so I can now run tests much more easily.
>

Okay, Thanks.

Claude
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Re: [PATCH 2/5] ASoC: S3C64XX: Add ADC source clock setting

[Seungwhan Youn]

On Fri, Aug 6, 2010 at 7:26 PM, Mark Brown
<broonie@opensource.wolfsonmicro.com> wrote:
> On Fri, Aug 06, 2010 at 09:21:04AM +0900, Seungwhan Youn wrote:
>> This patch adds ADC source clock setting to set wm8580 use ADC
>> source clock to ADC_MCLK.
>>
>> Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
>> ---
>>  sound/soc/s3c24xx/smdk64xx_wm8580.c |    6 ++++++
>
> This isn't a patch for S3C64xx, this is a patch for the SMDK boards.
>

Can I go-ahead this ADC_MCLK patches? or will you have a plan to
handle this also?

Claude
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Re: [PATCH 2/5] ASoC: S3C64XX: Add ADC source clock setting

[Mark Brown]

On Sat, Aug 07, 2010 at 01:28:47AM +0900, Seungwhan Youn wrote:
> On Fri, Aug 6, 2010 at 7:26 PM, Mark Brown

> > This isn't a patch for S3C64xx, this is a patch for the SMDK boards.

> Can I go-ahead this ADC_MCLK patches? or will you have a plan to
> handle this also?

Not really much point if we do the clocking properly - it changes over
to specifying the clock to via set_sysclk() so there's a code change
implied.

Re: [PATCH 2/5] ASoC: S3C64XX: Add ADC source clock setting

[Seungwhan Youn]

On Sat, Aug 7, 2010 at 1:49 AM, Mark Brown
<broonie@opensource.wolfsonmicro.com> wrote:
> On Sat, Aug 07, 2010 at 01:28:47AM +0900, Seungwhan Youn wrote:
>> On Fri, Aug 6, 2010 at 7:26 PM, Mark Brown
>
>> > This isn't a patch for S3C64xx, this is a patch for the SMDK boards.
>
>> Can I go-ahead this ADC_MCLK patches? or will you have a plan to
>> handle this also?
>
> Not really much point if we do the clocking properly - it changes over
> to specifying the clock to via set_sysclk() so there's a code change
> implied.
>

I see. Thank you Mark. ;-)

Claude

Re: [PATCH 1/5] ASoC: wm8580: Add to support ADC clock source setting

[Jassi Brar]

On Fri, Aug 6, 2010 at 7:19 PM, Mark Brown
<broonie@opensource.wolfsonmicro.com> wrote:
> On Fri, Aug 06, 2010 at 01:27:48PM +0900, Jassi Brar wrote:
>
>> This is OK. Though I don't remember why it wasn't accepted when
>> I submitted a few months ago.
>
> IIRC it was part of a larger patch or patch series which had other
> issues.
Yes you are right, seems I forgot to resubmit. My bad.