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[92.40.203.214]) by smtp.gmail.com with ESMTPSA id h17-20020a05600c351100b003973ea7e725sm3452720wmq.0.2022.07.08.08.32.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:32:47 -0700 (PDT) References: <20220708104304.51415-1-aidanmacdonald.0x0@gmail.com> <20220708104304.51415-5-aidanmacdonald.0x0@gmail.com> From: Aidan MacDonald To: Mark Brown Subject: Re: [PATCH v3 04/11] ASoC: jz4740-i2s: Handle independent FIFO flush bits Date: Fri, 08 Jul 2022 16:30:55 +0100 In-reply-to: Message-ID: MIME-Version: 1.0 Content-Type: text/plain Cc: alsa-devel@alsa-project.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, tiwai@suse.com, paul@crapouillou.net X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Mark Brown writes: > On Fri, Jul 08, 2022 at 11:42:57AM +0100, Aidan MacDonald wrote: >> On the JZ4740, there is a single bit that flushes (empties) both >> the transmit and receive FIFO. Later SoCs have independent flush >> bits for each FIFO, which allows us to flush the right FIFO when >> starting up a stream. >> >> This also fixes a bug: since we were only setting the JZ4740's >> flush bit, which corresponds to the TX FIFO flush bit on other >> SoCs, other SoCs were not having their RX FIFO flushed at all. >> >> Fixes: 967beb2e8777 ("ASoC: jz4740: Add jz4780 support") > > Fixes should generally be at the start of a patch series so they don't > end up depending on other patches needlessly. Okay then, I'll refactor it to allow for easier backporting.