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From: Dan Carpenter <dan.carpenter@oracle.com>
To: spujar@nvidia.com
Cc: alsa-devel@alsa-project.org
Subject: [bug report] ASoC: tegra: Add Tegra210 based OPE driver
Date: Mon, 13 Jun 2022 17:10:56 +0300	[thread overview]
Message-ID: <YqdFcPETMQGZm9AK@kili> (raw)

Hello Sameer Pujar,

The patch 7358a803c778: "ASoC: tegra: Add Tegra210 based OPE driver"
from Jun 3, 2022, leads to the following Smatch static checker
warning:

	sound/soc/tegra/tegra210_mbdrc.c:778 tegra210_mbdrc_hw_params()
	warn: bitwise AND condition is false here

sound/soc/tegra/tegra210_mbdrc.c
    769 int tegra210_mbdrc_hw_params(struct snd_soc_component *cmpnt)
    770 {
    771         struct tegra210_ope *ope = snd_soc_component_get_drvdata(cmpnt);
    772         const struct tegra210_mbdrc_config *conf = &mbdrc_init_config;
    773         u32 val = 0;
    774         unsigned int i;
    775 
    776         regmap_read(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, &val);
    777 
--> 778         if (val & TEGRA210_MBDRC_CFG_MBDRC_MODE_BYPASS)
                          ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

TEGRA210_MBDRC_CFG_MBDRC_MODE_BYPASS is zero so this can't be true.

#define TEGRA210_MBDRC_CFG_MBDRC_MODE_BYPASS            (0 << TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT)

The common false positive with this warning is that the macro is
something which depends on the .config and in that case I just add it
to the list in smatch_data/kernel.unconstant_macros.  But in this case
the macro is just always zero...  Is there a plan to make it
configurable or something?

    779                 return 0;
    780 
    781         for (i = 0; i < MBDRC_NUM_BAND; i++) {
    782                 const struct tegra210_mbdrc_band_params *params =
    783                         &conf->band_params[i];
    784 
    785                 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE;
    786 
    787                 tegra210_mbdrc_write_ram(ope->mbdrc_regmap,
    788                                          reg_off + TEGRA210_MBDRC_CFG_RAM_CTRL,
    789                                          reg_off + TEGRA210_MBDRC_CFG_RAM_DATA,
    790                                          0, (u32 *)&params->biquad_params[0],
    791                                          TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5);
    792         }
    793         return 0;
    794 }

regards,
dan carpenter

             reply	other threads:[~2022-06-13 14:12 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-13 14:10 Dan Carpenter [this message]
2022-06-14  4:17 ` [bug report] ASoC: tegra: Add Tegra210 based OPE driver Sameer Pujar
2022-06-14  6:09   ` Dan Carpenter
2022-06-15  4:46     ` Sameer Pujar

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