From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC4EEC0015E for ; Sat, 22 Jul 2023 17:11:02 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id DBE12DF6; Sat, 22 Jul 2023 19:10:10 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz DBE12DF6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1690045860; bh=cOfUxXcWLzgkeJxmqNK7OCnsanQANi9jac3/hEWsLfw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-Id: List-Archive:List-Help:List-Owner:List-Post:List-Subscribe: List-Unsubscribe:From; b=jnDGP5xyru2ikzBbISvVnX6o4JU9t/5tMmFFCs4AygdMJI2BuwjKqxMM5SSHCxFwN YWZIeNzvh6RLmwJAyODmRtnUNf3JQ/lc0jllsankPsb8n0VdrmRNuSOaYegvdgqFjr xRb1hn8RgWanPMb4FVp7+XtaCkm3UjLtd9BdzL44= Received: by alsa1.perex.cz (Postfix, from userid 50401) id F0EB2F8061C; Sat, 22 Jul 2023 19:06:04 +0200 (CEST) Received: from mailman-core.alsa-project.org (mailman-core.alsa-project.org [10.254.200.10]) by alsa1.perex.cz (Postfix) with ESMTP id 1D184F8061B; Sat, 22 Jul 2023 19:06:04 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 95DA3F8047D; Fri, 21 Jul 2023 17:59:27 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id B0E0CF8007E for ; Fri, 21 Jul 2023 17:59:15 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz B0E0CF8007E X-IronPort-AV: E=McAfee;i="6600,9927,10778"; a="397947185" X-IronPort-AV: E=Sophos;i="6.01,222,1684825200"; d="scan'208";a="397947185" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2023 08:59:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10778"; a="1055599368" X-IronPort-AV: E=Sophos;i="6.01,222,1684825200"; d="scan'208";a="1055599368" Received: from smile.fi.intel.com ([10.237.72.54]) by fmsmga005.fm.intel.com with ESMTP; 21 Jul 2023 08:58:59 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.96) (envelope-from ) id 1qMsWt-00BQxg-0w; Fri, 21 Jul 2023 18:58:55 +0300 Date: Fri, 21 Jul 2023 18:58:55 +0300 From: Andy Shevchenko To: nikita.shubin@maquefel.me Cc: Hartley Sweeten , Lennert Buytenhek , Alexander Sverdlin , Russell King , Lukasz Majewski , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Daniel Lezcano , Thomas Gleixner , Alessandro Zummo , Alexandre Belloni , Wim Van Sebroeck , Guenter Roeck , Sebastian Reichel , Thierry Reding , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Mark Brown , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vinod Koul , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Damien Le Moal , Sergey Shtylyov , Dmitry Torokhov , Arnd Bergmann , Olof Johansson , soc@kernel.org, Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Michael Peters , Kris Bahnsen , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-rtc@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-pm@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, linux-mtd@lists.infradead.org, linux-ide@vger.kernel.org, linux-input@vger.kernel.org, alsa-devel@alsa-project.org Subject: Re: [PATCH v3 09/42] clocksource: ep93xx: Add driver for Cirrus Logic EP93xx Message-ID: References: <20230605-ep93xx-v3-0-3d63a5f1103e@maquefel.me> <20230605-ep93xx-v3-9-3d63a5f1103e@maquefel.me> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230605-ep93xx-v3-9-3d63a5f1103e@maquefel.me> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-MailFrom: andy@kernel.org X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1 Message-ID-Hash: KWJMX26CRZWM3RTPR2T7DYS2UQFTXIYX X-Message-ID-Hash: KWJMX26CRZWM3RTPR2T7DYS2UQFTXIYX X-Mailman-Approved-At: Sat, 22 Jul 2023 17:04:41 +0000 X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: On Thu, Jul 20, 2023 at 02:29:09PM +0300, Nikita Shubin via B4 Relay wrote: > From: Nikita Shubin > > This us a rewrite of EP93xx timer driver in > arch/arm/mach-ep93xx/timer-ep93xx.c trying to do everything > the device tree way: > > - Make every IO-access relative to a base address and dynamic > so we can do a dynamic ioremap and get going. > - Find register range and interrupt from the device tree. ... + bits.h > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include ... > +/************************************************************************* Won't you marc it as a DOC: section? > + * Timer handling for EP93xx > + ************************************************************************* > + * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and > + * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate > + * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, > + * is free-running, and can't generate interrupts. > + * > + * The 508 kHz timers are ideal for use for the timer interrupt, as the > + * most common values of HZ divide 508 kHz nicely. We pick the 32 bit > + * timer (timer 3) to get as long sleep intervals as possible when using > + * CONFIG_NO_HZ. > + * > + * The higher clock rate of timer 4 makes it a better choice than the > + * other timers for use as clock source and for sched_clock(), providing > + * a stable 40 bit time base. > + ************************************************************************* > + */ ... > +/* > + * This read-only register contains the low word of the time stamp debug timer > + * ( Timer4). When this register is read, the high byte of the Timer4 counter is One too many spaces. > + * saved in the Timer4ValueHigh register. > + */ ... > +static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) > +{ > + struct ep93xx_tcu *tcu = ep93xx_tcu; > + struct clock_event_device *evt = dev_id; > + > + /* Writing any value clears the timer interrupt */ > + writel(1, tcu->base + EP93XX_TIMER3_CLEAR); Would 0 suffice? > + evt->event_handler(evt); > + > + return IRQ_HANDLED; > +} ... > +static int __init ep93xx_timer_of_init(struct device_node *np) > +{ > + int irq; > + unsigned long flags = IRQF_TIMER | IRQF_IRQPOLL; > + struct ep93xx_tcu *tcu; > + int ret; > + > + tcu = kzalloc(sizeof(*tcu), GFP_KERNEL); > + if (!tcu) > + return -ENOMEM; > + > + tcu->base = of_iomap(np, 0); fwnode_iomap()? See below why it might make sense. > + if (!tcu->base) { > + pr_err("Can't remap registers\n"); First of all, you may utilize pr_fmt(). Second, you may add %pOF for better user experience. > + ret = -ENXIO; > + goto out_free; > + } > + irq = irq_of_parse_and_map(np, 0); fwnode_irq_get() which is better in terms of error handling. > + if (irq == 0) > + irq = -EINVAL; > + if (irq < 0) { > + pr_err("EP93XX Timer Can't parse IRQ %d", irq); As per above. > + goto out_free; > + } ... > +} -- With Best Regards, Andy Shevchenko