From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
To: Daniel Baluta <daniel.baluta@gmail.com>
Cc: Linux-ALSA <alsa-devel@alsa-project.org>,
andriy.shevchenko@intel.com, Takashi Iwai <tiwai@suse.de>,
Pan Xiuli <xiuli.pan@linux.intel.com>,
Liam Girdwood <liam.r.girdwood@linux.intel.com>,
vkoul@kernel.org, Mark Brown <broonie@kernel.org>,
sound-open-firmware@alsa-project.org,
Rander Wang <rander.wang@linux.intel.com>,
Alan Cox <alan@linux.intel.com>
Subject: Re: [Sound-open-firmware] [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support.
Date: Fri, 18 Jan 2019 10:14:25 -0600 [thread overview]
Message-ID: <a49e3fd6-4e2f-907a-a5a6-825e2ebf22ad@linux.intel.com> (raw)
In-Reply-To: <CAEnQRZCRrt_D2wRtGVBBFtio6VZuB-cVaJMQU3GOZujypqU+Xw@mail.gmail.com>
> I have few things to bring into discussion now, perhaps you can comment on it.
>
> Firstly, we might want to look at the mailbox controller
> (drivers/mailbox/mailbox.c).
> It looks like the communication from AP (application processor) and
> the DSP uses shim + mailbox
> in Intel implementation, which could be abstracted by a mailbox client.
>
> The confusing part here is the naming. In the Linux kernel the shim
> layer you use is abstracted
> by the mailbox controller, while mailbox from Intel implementation is
> really a shared memory area.
>
> We have this already implemented for our mailbox (Messaging Unit) in
> drivers/mailbox/imx-mailbox.c and
> trying to integrate with SOF.
>
> So, for IPC we have the following "naming" differences:
> * imx mailbox MU - equivalent with SHIM layer from Intel SOF.
> * imx shared memory - equivalent with mailbox layer from Intel SOF.
the "shim" on the intel side is a mix of control capabilities. There are
indeed IPC registers in there, but also clock, DMA and power control
capabilities. I am not sure we can really remove direct access to the
shim, it's really the host-visible set of DSP registers.
We'll look at the pointer to the i.mx mailbox, thanks for the information.
>
> Secondly, the "doorbell" naming of the interrupts. It surely looks
> like a doorbell because we notify the
> DSP that we pushed some data in a shared memory area. Anyhow, besides
> pushing data to the shared
> memory area we also send some data with the notification too.
>
> For example, in byt_send_msg we do:
>
> sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, msg->msg_size);
> snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, cmd | SHIM_BYT_IPCX_BUSY);
>
> Not sure how cmd is used on the DSP side. Anyhow, this is not really
> important for the next version
> of the patches. Just wanted to hear your opinion.
Humm, that one looks like an exception as well, it makes no sense. This
is over a year old. Liam, any memories of this?
next prev parent reply other threads:[~2019-01-18 16:14 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-11 21:30 [PATCH 00/21] Sound Open Firmware (SOF) - Intel support Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 01/21] ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support Pierre-Louis Bossart
2018-12-12 4:08 ` Takashi Sakamoto
2018-12-12 14:45 ` Pierre-Louis Bossart
2018-12-12 19:24 ` [Sound-open-firmware] " Pierre-Louis Bossart
[not found] ` <b8db627a-bd32-34d7-b45b-aeb2206b2b17@linux.intel.com>
2018-12-17 13:40 ` Yang, Libin
2019-01-18 8:14 ` Daniel Baluta
2019-01-18 15:02 ` [Sound-open-firmware] " Pierre-Louis Bossart
2019-01-18 15:29 ` Daniel Baluta
2019-01-18 16:14 ` Pierre-Louis Bossart [this message]
2019-01-22 7:35 ` Daniel Baluta
2019-01-22 16:22 ` Pierre-Louis Bossart
2019-01-22 16:49 ` Daniel Baluta
2018-12-11 21:30 ` [PATCH 02/21] ASoC: SOF: Intel: Add HSW HW DSP support Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 03/21] ASoC: SOF: Intel: Add support for BDW " Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 04/21] ASoC: SOF: Intel: Add APL/CNL " Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 05/21] ASoC: SOF: Intel: Add HDA controller for Intel DSP Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 06/21] ASoC: SOF: Intel: Add Intel specific HDA DSP HW operations Pierre-Louis Bossart
2018-12-12 12:04 ` Takashi Iwai
2018-12-12 14:48 ` Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 07/21] ASoC: SOF: Intel: Add Intel specific HDA IPC mechanisms Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 08/21] ASoC: SOF: Intel: Add Intel specific HDA firmware loader Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 09/21] ASoC: SOF: Intel: Add Intel specific HDA PCM operations Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 10/21] ASoC: SOF: Intel: Add hda-bus support and initialization Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 11/21] ASoC: SOF: Intel: Add Intel specific HDA stream operations Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 12/21] ASoC: SOF: Intel: Add Intel specific HDA trace operations Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 13/21] ASoC: SOF: Intel: Add support for HDAudio codecs Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 14/21] ASoC: SOF: Intel: SKL, CNL, APL platform DAIs Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 15/21] ASoC: SOF: Intel: Add platform differentiation for SKL, APL and CNL Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 16/21] ASoC: SOF: Intel: Add SKL-specific code loader Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 17/21] ASoC: SOF: Add ACPI device support Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 18/21] ASoC: SOF: Add PCI " Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 19/21] ALSA: HDA: export process_unsol_events() Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 20/21] ASoC: Intel: Kconfig: expose common option between SST and SOF drivers Pierre-Louis Bossart
2018-12-11 21:30 ` [PATCH 21/21] ASoC: SOF: Add Build support for SOF core and Intel drivers Pierre-Louis Bossart
2018-12-12 11:50 ` Takashi Iwai
2018-12-12 14:51 ` Pierre-Louis Bossart
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