From: Liam Girdwood <liam.r.girdwood@linux.intel.com>
To: Cezary Rojewski <cezary.rojewski@intel.com>
Cc: alsa-devel@alsa-project.org,
Christian Bundy <christianbundy@fraction.io>,
yang.jie@linux.intel.com, zwisler@google.com,
pierre-louis.bossart@linux.intel.com, broonie@kernel.org
Subject: Re: [bug report] 'ASoC: Intel: haswell: Power transition refactor' and PulseAudio
Date: Tue, 01 Sep 2020 21:31:13 +0100 [thread overview]
Message-ID: <a4b2783c7ae274c752c8d2322e535006f6c46c1f.camel@linux.intel.com> (raw)
In-Reply-To: <c93c0522-d8b7-e4c4-b11b-80646cfd0432@intel.com>
On Tue, 2020-09-01 at 17:37 +0200, Cezary Rojewski wrote:
> > > Thank you for report! Issue is a known one to us and has already
> > > been
> > > addressed by:
> > > [PATCH v4 00/13] ASoC: Intel: Catpt - Lynx and Wildcat
> > > point
> > > https://www.spinics.net/lists/alsa-devel/msg113762.html
> > > waiting for final dependency to be merged (Andy's resource-API
> > > changes,
> > > as Mark already added the SPI ones) so v5 with review changes can
> > > be
> > > provided. Shouldn't be long before this gets merged. As
> > > consequence,
> > > /haswell/ ceases to exist.
> > Please also don't forget that the new BDW HW register programming
> > flows
> > need to be shared as common code with the SOF BDW driver.
> > Thanks
> > Liam
>
>
> I don't believe this is related to Christian's report.
To be clear, it's related to v5 readiness statement and not this
report.
Thanks
Liam
prev parent reply other threads:[~2020-09-01 20:32 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-31 21:55 [bug report] 'ASoC: Intel: haswell: Power transition refactor' and PulseAudio Christian Bundy
2020-09-01 11:33 ` Cezary Rojewski
2020-09-01 13:38 ` Pierre-Louis Bossart
2020-09-01 14:11 ` Cezary Rojewski
2020-09-01 15:23 ` Liam Girdwood
2020-09-01 15:37 ` Cezary Rojewski
2020-09-01 17:25 ` Christian Bundy
2020-09-01 20:31 ` Liam Girdwood [this message]
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