[PATCH RESEND 0/4] ASoC: fsl_esai: Fix some issues

[Nicolin Chen <Guangyu.Chen@freescale.com>]

Sorry for this resend. I just found my previous patches have
not been delivered successfully to the alsa maillist.

This series of patches fix the following problems:
PATCH-1 for an incorrect ratio range check.
PATCH-2 for an incorrect bypass settings of FSYS clock source.
PATCH-3 for duplicated calculations and configurations of dividers
PATCH-4 for mismatched init flow of configuration comparing to RM.

Nicolin Chen (4):
  ASoC: fsl_esai: Fix incorrect condition within ratio range check for
    FP
  ASoC: fsl_esai: Only bypass sck_div for EXTAL source
  ASoC: fsl_esai: Bypass divider settings if clock requirement is not
    changed
  ASoC: fsl_esai: Set PCRC and PRRC registers at the end of hw_params()

 sound/soc/fsl/fsl_esai.c | 45 ++++++++++++++++++++++++++++++++++-----------
 1 file changed, 34 insertions(+), 11 deletions(-)

-- 
1.8.4